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Message-ID: <CAFp+6iF-N63YSsdv2a6=MYp_mD=eQY_Oi8=9JVNU5dG0BA7YGQ@mail.gmail.com>
Date:	Mon, 24 Nov 2014 10:30:19 +0530
From:	Vivek Gautam <gautamvivek1987@...il.com>
To:	Alim Akhtar <alim.akhtar@...il.com>
Cc:	Vivek Gautam <gautam.vivek@...sung.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-samsung-soc@...r.kernel.org" 
	<linux-samsung-soc@...r.kernel.org>,
	Linux USB Mailing List <linux-usb@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	Felipe Balbi <balbi@...com>, kishon <kishon@...com>,
	"linux-omap@...r.kernel.org" <linux-omap@...r.kernel.org>,
	Greg KH <gregkh@...uxfoundation.org>,
	Tomasz Figa <tomasz.figa@...il.com>,
	Sylwester Nawrocki <s.nawrocki@...sung.com>,
	"robh+dt" <robh+dt@...nel.org>,
	Alan Stern <stern@...land.harvard.edu>,
	Kukjin Kim <kgene.kim@...sung.com>,
	Linus Walleij <linus.walleij@...aro.org>
Subject: Re: [PATCH 01/11] pinctrl: exynos: Add BUS1 pin controller for exynos7

Hi Alim,


On Sat, Nov 22, 2014 at 7:07 PM, Alim Akhtar <alim.akhtar@...il.com> wrote:
> Hi Vivek,
>
> On Fri, Nov 21, 2014 at 7:05 PM, Vivek Gautam <gautam.vivek@...sung.com> wrote:
>> USB and Power regulator on Exynos7 require gpios available
>> in BUS1 pin controller block.
>> So adding the BUS1 pinctrl support.
>>
>> Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@...il.com>
>> Signed-off-by: Vivek Gautam <gautam.vivek@...sung.com>
>> Cc: Linus Walleij <linus.walleij@...aro.org>
>> ---
>>  drivers/pinctrl/samsung/pinctrl-exynos.c |   12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
>> index d5d4cfc..caca5b5 100644
>> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
>> @@ -1300,6 +1300,13 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
>>         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
>>  };
>>
>> +/* pin banks of exynos7 pin-controller - BUS1 */
>> +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
>> +       EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
>> +       EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
>> +};
>> +
> Looks like you are just trying to touch pin banks only related to USB
> stuffs, but as this patch does not have any dependencies on other
> patches in this series, will you consider adding other pin banks of
> BUS1, just for completeness of BUS1 pin-controller.

True, this just touches the USB related pinctrl.
Will add the rest pin banks of BUS1 for completeness.
Thanks for pointing out. :-)

[snip]



-- 
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India
--
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