linux-kernel - Re: [PATCH V4] arm64: amd-seattle: Adding device tree for AMD Seattle platform

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Message-ID: <547458B9.2000805@arm.com>
Date:	Tue, 25 Nov 2014 10:23:53 +0000
From:	Marc Zyngier <marc.zyngier@....com>
To:	"suravee.suthikulpanit@....com" <suravee.suthikulpanit@....com>,
	"arnd@...db.de" <arnd@...db.de>,
	Mark Rutland <Mark.Rutland@....com>,
	Will Deacon <Will.Deacon@....com>,
	Catalin Marinas <Catalin.Marinas@....com>
CC:	"robherring2@...il.com" <robherring2@...il.com>,
	Liviu Dudau <Liviu.Dudau@....com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"arm@...nel.org" <arm@...nel.org>,
	Thomas Lendacky <Thomas.Lendacky@....com>,
	Joel Schopp <Joel.Schopp@....com>
Subject: Re: [PATCH V4] arm64: amd-seattle: Adding device tree for AMD Seattle
 platform

Hi Suravee,

Just spotted a small issue below (looks like a recurring mistake in a
number of DTs I've seem lately):

On 24/11/14 21:51, suravee.suthikulpanit@....com wrote:
> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
> 
> Initial revision of device tree for AMD Seattle platform.
> 
> Cc: Arnd Bergmann <arnd@...db.de>
> Cc: Marc Zyngier <marc.zyngier@....com>
> Cc: Mark Rutland <mark.rutland@....com>
> Cc: Will Deacon <will.deacon@....com>
> Cc: Catalin Marinas <catalin.marinas@....com>
> Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
> Signed-off-by: Thomas Lendacky <Thomas.Lendacky@....com>
> Signed-off-by: Joel Schopp <Joel.Schopp@....com>
> ---
> V4 Changes:
>     * Remove unnecessary smb layer and move motherbord to top level
>     * Move include dtsi to top level
>     * Remove apb_pclk from sata0 and i2c
>     * Fix GIC Virtual Maintanance Interrupt from PPI24 (8) to PPI25 (9)
>     * Add 40-bit dma-ranges for motherboard (simple-bus)
>     * Remove dma0 (pl330) entry for now since it only supports 32-bit DMA.
>       It is basically not used at the moment. It would also need SMMU
>       to allow dma remapping to 40-bit DMA range.
>     * Add phandle spi0 and spi1
>     * Hook up gpio0 pin 7 with MMC Card Detection (CD) support.
>     * Changes in pcie0 entry:
>         - Add 40-bit dma-ranges
>         - Remove interrupts property
>         - Add interrupt-map/mask property
>         - Fix PCI I/O range 
>         - Merge PCI 32-bit ranges
>         - Merge PCI 64-bit ranges
> 
> NOTE: I am not add a new compatible ID for the sata0 as Rob Herring
>       suggested since there is no need at the momement, and I am trying
>       to avoid introducing ID unnecessarily.
> 
>  arch/arm64/Kconfig                          |   5 +
>  arch/arm64/boot/dts/Makefile                |   1 +
>  arch/arm64/boot/dts/amd-seattle-periph.dtsi | 156 ++++++++++++++++++++++++++++
>  arch/arm64/boot/dts/amd-seattle.dts         |  89 ++++++++++++++++
>  4 files changed, 251 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/amd-seattle-periph.dtsi
>  create mode 100644 arch/arm64/boot/dts/amd-seattle.dts
> 

[...]

> diff --git a/arch/arm64/boot/dts/amd-seattle.dts b/arch/arm64/boot/dts/amd-seattle.dts
> new file mode 100644
> index 0000000..d5fc482
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amd-seattle.dts
> @@ -0,0 +1,89 @@
> +/*
> + * DTS file for AMD Seattle
> + *
> + * Copyright (C) 2014 Advanced Micro Devices, Inc.
> + */
> +
> +/dts-v1/;
> +
> +/include/ "amd-seattle-periph.dtsi"
> +
> +/ {
> +	compatible = "amd,seattle";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	chosen {
> +		stdout-path = &serial0;
> +		linux,pci-probe-only;
> +	};
> +
> +	gic: interrupt-controller@...01000 {
> +		compatible = "arm,gic-400", "arm,cortex-a15-gic";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		reg = <0x0 0xe1110000 0 0x1000>,
> +		      <0x0 0xe112f000 0 0x2000>,
> +		      <0x0 0xe1140000 0 0x10000>,
> +		      <0x0 0xe1160000 0 0x10000>;
> +		interrupts = <1 9 0xf04>;
> +		ranges;
> +		v2m0: v2m@...80000 {
> +			compatible = "arm,gic-v2m-frame";
> +			msi-controller;
> +			arm,msi-base-spi = <64>;
> +			arm,msi-num-spis = <256>;
> +			reg = <0x0 0xe1180000 0 0x1000>;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <1 13 0xff01>,
> +			     <1 14 0xff01>,
> +			     <1 11 0xff01>,
> +			     <1 10 0xff01>;
> +	};

The Cortex-A57 TRM clearly states that these interrupts are level triggered.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...
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