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Message-id: <1417073716-22997-12-git-send-email-cw00.choi@samsung.com>
Date: Thu, 27 Nov 2014 16:35:08 +0900
From: Chanwoo Choi <cw00.choi@...sung.com>
To: linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: kgene.kim@...sung.com, mark.rutland@....com, arnd@...db.de,
olof@...om.net, catalin.marinas@....com, will.deacon@....com,
s.nawrocki@...sung.com, tomasz.figa@...il.com,
thomas.abraham@...aro.org, linus.walleij@...aro.org,
kyungmin.park@...sung.com, inki.dae@...sung.com,
chanho61.park@...sung.com, geunsik.lim@...sung.com,
sw0312.kim@...sung.com, jh80.chung@...sung.com,
cw00.choi@...sung.com, a.kesavan@...sung.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: [PATCH 11/19] clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2}
domains
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and used for regiser accesses.
Cc: Sylwester Nawrocki <s.nawrocki@...sung.com>
Cc: Tomasz Figa <tomasz.figa@...il.com>
Signed-off-by: Chanwoo Choi <cw00.choi@...sung.com>
Acked-by: Inki Dae <inki.dae@...sung.com>
Acked-by: Geunsik Lim <geunsik.lim@...sung.com>
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 21 ++
drivers/clk/samsung/clk-exynos5433.c | 225 ++++++++++++++++++++-
include/dt-bindings/clock/exynos5433.h | 52 ++++-
3 files changed, 295 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index 9a6ae75..03ae40a 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -25,6 +25,9 @@ Required Properties:
which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
which generates clocks for Cortex-A5/BUS/AUDIO clocks.
+ - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
+ and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
+ which generates global data buses clock and global peripheral buses clock.
- reg: physical base address of the controller and length of memory mapped
region.
@@ -94,6 +97,24 @@ Example 1: Examples of clock controller nodes are listed below.
#clock-cells = <1>;
};
+ cmu_bus0: clock-controller@...3600000 {
+ compatible = "samsung,exynos5433-cmu-bus0";
+ reg = <0x13600000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_bus1: clock-controller@...4800000 {
+ compatible = "samsung,exynos5433-cmu-bus1";
+ reg = <0x14800000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
+ cmu_bus2: clock-controller@...3400000 {
+ compatible = "samsung,exynos5433-cmu-bus2";
+ reg = <0x13400000 0x0b04>;
+ #clock-cells = <1>;
+ };
+
Example 2: UART controller node that consumes the clock generated by the clock
controller.
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 9f28672..f0975e1 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -428,7 +428,7 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
DIV_TOP2, 0, 3),
/* DIV_TOP3 */
- DIV(CLK_DIV_ACLK_IMEM_SSSX, "div_aclk_imem_sssx",
+ DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
"mout_bus_pll_user", DIV_TOP3, 24, 3),
DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
"mout_bus_pll_user", DIV_TOP3, 20, 3),
@@ -443,6 +443,14 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
"mout_bus_pll_user", DIV_TOP3, 0, 3),
+ /* DIV_TOP4 */
+ DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
+ DIV_TOP4, 8, 3),
+ DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
+ DIV_TOP4, 4, 3),
+ DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
+ DIV_TOP4, 0, 3),
+
/* DIV_TOP_FSYS0 */
DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
DIV_TOP_FSYS0, 16, 8),
@@ -506,6 +514,19 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
static struct samsung_gate_clock top_gate_clks[] __initdata = {
/* ENABLE_ACLK_TOP */
+ GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
+ ENABLE_ACLK_TOP, 30, 0, 0),
+ GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
+ "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
+ 29, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
+ ENABLE_ACLK_TOP, 26, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
+ ENABLE_ACLK_TOP, 25, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
+ ENABLE_ACLK_TOP, 24, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
+ ENABLE_ACLK_TOP, 23, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
ENABLE_ACLK_TOP, 22, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
@@ -2629,3 +2650,205 @@ static void __init exynos5433_cmu_aud_init(struct device_node *np)
}
CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
exynos5433_cmu_aud_init);
+
+
+/*
+ * Register offset definitions for CMU_BUS0
+ */
+#define DIV_BUS0 0x0600
+#define DIV_STAT_BUS0 0x0700
+#define ENABLE_ACLK_BUS0 0x0800
+#define ENABLE_PCLK_BUS0 0x0900
+#define ENABLE_IP_BUS0 0x0b00
+#define ENABLE_IP_BUS1 0x0b04
+
+static unsigned long bus0_clk_regs[] __initdata = {
+ DIV_BUS0,
+ DIV_STAT_BUS0,
+ ENABLE_ACLK_BUS0,
+ ENABLE_PCLK_BUS0,
+ ENABLE_IP_BUS0,
+ ENABLE_IP_BUS1,
+};
+
+static struct samsung_div_clock bus0_div_clks[] __initdata = {
+ /* DIV_BUS0 */
+ DIV(CLK_DIV_PCLK_BUS0_133, "div_pclk_bus0_133", "aclk_bus0_400",
+ DIV_BUS0, 0, 3),
+};
+
+static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_BUS0 */
+ GATE(CLK_ACLK_AHB2APB_BUS0P, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
+ ENABLE_ACLK_BUS0, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS0NP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
+ ENABLE_ACLK_BUS0, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS0ND_400, "aclk_bus0nd_400", "aclk_bus0_400",
+ ENABLE_ACLK_BUS0, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_BUS0 */
+ GATE(CLK_PCLK_BUS0SRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
+ ENABLE_PCLK_BUS0, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_BUS0, "pclk_pmu_bus0", "div_pclk_bus0_133",
+ ENABLE_PCLK_BUS0, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_BUS0, "pclk_sysreg_bus0", "div_pclk_bus0_133",
+ ENABLE_PCLK_BUS0, 0, 0, 0),
+};
+
+static struct samsung_cmu_info bus0_cmu_info __initdata = {
+ .div_clks = bus0_div_clks,
+ .nr_div_clks = ARRAY_SIZE(bus0_div_clks),
+ .gate_clks = bus0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(bus0_gate_clks),
+ .nr_clk_ids = BUS0_NR_CLK,
+ .clk_regs = bus0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(bus0_clk_regs),
+};
+
+static void __init exynos5433_cmu_bus0_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &bus0_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_bus0, "samsung,exynos5433-cmu-bus0",
+ exynos5433_cmu_bus0_init);
+
+/*
+ * Register offset definitions for CMU_BUS1
+ */
+#define DIV_BUS1 0x0600
+#define DIV_STAT_BUS1 0x0700
+#define ENABLE_ACLK_BUS1 0x0800
+#define ENABLE_PCLK_BUS1 0x0900
+#define ENABLE_IP_BUS10 0x0b00
+#define ENABLE_IP_BUS11 0x0b04
+
+static unsigned long bus1_clk_regs[] __initdata = {
+ DIV_BUS1,
+ DIV_STAT_BUS1,
+ ENABLE_ACLK_BUS1,
+ ENABLE_PCLK_BUS1,
+ ENABLE_IP_BUS10,
+ ENABLE_IP_BUS11,
+};
+
+static struct samsung_div_clock bus1_div_clks[] __initdata = {
+ /* DIV_BUS1 */
+ DIV(CLK_DIV_PCLK_BUS1_133, "div_pclk_bus1_133", "aclk_bus1_400",
+ DIV_BUS1, 0, 3),
+};
+
+static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_BUS1 */
+ GATE(CLK_ACLK_AHB2APB_BUS1P, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
+ ENABLE_ACLK_BUS1, 4, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS1NP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
+ ENABLE_ACLK_BUS1, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS1ND_400, "aclk_bus1nd_400", "aclk_bus1_400",
+ ENABLE_ACLK_BUS1, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_BUS1 */
+ GATE(CLK_PCLK_BUS1SRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
+ ENABLE_PCLK_BUS1, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_BUS1, "pclk_pmu_bus1", "div_pclk_bus1_133",
+ ENABLE_PCLK_BUS1, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_BUS1, "pclk_sysreg_bus1", "div_pclk_bus1_133",
+ ENABLE_PCLK_BUS1, 0, 0, 0),
+};
+
+static struct samsung_cmu_info bus1_cmu_info __initdata = {
+ .div_clks = bus1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(bus1_div_clks),
+ .gate_clks = bus1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(bus1_gate_clks),
+ .nr_clk_ids = BUS1_NR_CLK,
+ .clk_regs = bus1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(bus1_clk_regs),
+};
+
+static void __init exynos5433_cmu_bus1_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &bus1_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_bus1, "samsung,exynos5433-cmu-bus1",
+ exynos5433_cmu_bus1_init);
+
+/*
+ * Register offset definitions for CMU_BUS2
+ */
+#define MUX_SEL_BUS2 0x0200
+#define MUX_ENABLE_BUS2 0x0300
+#define MUX_STAT_BUS2 0x0400
+#define DIV_BUS2 0x0600
+#define DIV_STAT_BUS2 0x0700
+#define ENABLE_ACLK_BUS2 0x0800
+#define ENABLE_PCLK_BUS2 0x0900
+#define ENABLE_IP_BUS20 0x0b00
+#define ENABLE_IP_BUS21 0x0b04
+
+static unsigned long bus2_clk_regs[] __initdata = {
+ MUX_SEL_BUS2,
+ MUX_ENABLE_BUS2,
+ MUX_STAT_BUS2,
+ DIV_BUS2,
+ DIV_STAT_BUS2,
+ ENABLE_ACLK_BUS2,
+ ENABLE_PCLK_BUS2,
+ ENABLE_IP_BUS20,
+ ENABLE_IP_BUS21,
+};
+
+/* list of all parent clock list */
+PNAME(mout_aclk_bus2_400_p) = { "fin_pll", "aclk_bus2_400", };
+
+static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
+ /* MUX_SEL_BUS2 */
+ MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
+ mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
+};
+
+static struct samsung_div_clock bus2_div_clks[] __initdata = {
+ /* DIV_BUS2 */
+ DIV(CLK_DIV_PCLK_BUS2_133, "div_pclk_bus2_133",
+ "mout_aclk_bus2_400_user", DIV_BUS2, 0, 3),
+};
+
+static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
+ /* ENABLE_ACLK_BUS2 */
+ GATE(CLK_ACLK_AHB2APB_BUS2P, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
+ ENABLE_ACLK_BUS2, 3, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS2NP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
+ ENABLE_ACLK_BUS2, 2, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
+ "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS2,
+ 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
+ "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS2,
+ 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_BUS2 */
+ GATE(CLK_PCLK_BUS2SRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
+ ENABLE_PCLK_BUS2, 2, 0, 0),
+ GATE(CLK_PCLK_PMU_BUS2, "pclk_pmu_bus2", "div_pclk_bus2_133",
+ ENABLE_PCLK_BUS2, 1, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_PCLK_SYSREG_BUS2, "pclk_sysreg_bus2", "div_pclk_bus2_133",
+ ENABLE_PCLK_BUS2, 0, 0, 0),
+};
+
+static struct samsung_cmu_info bus2_cmu_info __initdata = {
+ .mux_clks = bus2_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
+ .div_clks = bus2_div_clks,
+ .nr_div_clks = ARRAY_SIZE(bus2_div_clks),
+ .gate_clks = bus2_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(bus2_gate_clks),
+ .nr_clk_ids = BUS2_NR_CLK,
+ .clk_regs = bus2_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
+};
+
+static void __init exynos5433_cmu_bus2_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &bus2_cmu_info);
+}
+CLK_OF_DECLARE(exynos5433_cmu_bus2, "samsung,exynos5433-cmu-bus2",
+ exynos5433_cmu_bus2_init);
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index e1c848a..56eb8c8 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -72,7 +72,7 @@
#define CLK_MOUT_SCLK_HDMI_SPDIF 64
#define CLK_DIV_ACLK_FSYS_200 100
-#define CLK_DIV_ACLK_IMEM_SSSX 101
+#define CLK_DIV_ACLK_IMEM_SSSX_266 101
#define CLK_DIV_ACLK_IMEM_200 102
#define CLK_DIV_ACLK_IMEM_266 103
#define CLK_DIV_ACLK_PERIC_66_B 104
@@ -108,6 +108,9 @@
#define CLK_DIV_ACLK_MFC_400 134
#define CLK_DIV_ACLK_G2D_266 135
#define CLK_DIV_ACLK_G2D_400 136
+#define CLK_DIV_ACLK_G3D_400 137
+#define CLK_DIV_ACLK_BUS0_400 138
+#define CLK_DIV_ACLK_BUS1_400 139
#define CLK_ACLK_PERIC_66 200
#define CLK_ACLK_PERIS_66 201
@@ -131,8 +134,14 @@
#define CLK_SCLK_AUDIO0 219
#define CLK_ACLK_G2D_266 220
#define CLK_ACLK_G2D_400 221
+#define CLK_ACLK_G3D_400 222
+#define CLK_ACLK_IMEM_SSX_266 223
+#define CLK_ACLK_BUS0_400 224
+#define CLK_ACLK_BUS1_400 225
+#define CLK_ACLK_IMEM_200 226
+#define CLK_ACLK_IMEM_266 227
-#define TOP_NR_CLK 222
+#define TOP_NR_CLK 228
/* CMU_CPIF */
#define CLK_FOUT_MPHY_PLL 1
@@ -680,4 +689,43 @@
#define AUD_NR_CLK 48
+/* CMU_BUS0 */
+#define CLK_DIV_PCLK_BUS0_133 1
+
+#define CLK_ACLK_AHB2APB_BUS0P 2
+#define CLK_ACLK_BUS0NP_133 3
+#define CLK_ACLK_BUS0ND_400 4
+#define CLK_PCLK_BUS0SRVND_133 5
+#define CLK_PCLK_PMU_BUS0 6
+#define CLK_PCLK_SYSREG_BUS0 7
+
+#define BUS0_NR_CLK 8
+
+/* CMU_BUS1 */
+#define CLK_DIV_PCLK_BUS1_133 1
+
+#define CLK_ACLK_AHB2APB_BUS1P 2
+#define CLK_ACLK_BUS1NP_133 3
+#define CLK_ACLK_BUS1ND_400 4
+#define CLK_PCLK_BUS1SRVND_133 5
+#define CLK_PCLK_PMU_BUS1 6
+#define CLK_PCLK_SYSREG_BUS1 7
+
+#define BUS1_NR_CLK 8
+
+/* CMU_BUS2 */
+#define CLK_MOUT_ACLK_BUS2_400_USER 1
+
+#define CLK_DIV_PCLK_BUS2_133 2
+
+#define CLK_ACLK_AHB2APB_BUS2P 3
+#define CLK_ACLK_BUS2NP_133 4
+#define CLK_ACLK_BUS2BEND_400 5
+#define CLK_ACLK_BUS2RTND_400 6
+#define CLK_PCLK_BUS2SRVND_133 7
+#define CLK_PCLK_PMU_BUS2 8
+#define CLK_PCLK_SYSREG_BUS2 9
+
+#define BUS2_NR_CLK 10
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
--
1.8.5.5
--
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