linux-kernel - [PATCH v4 0/2] Add support for the rockchip mmc clock phases using the framework

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Message-Id: <1417051827-12564-1-git-send-email-amstan@chromium.org>
Date:	Wed, 26 Nov 2014 17:30:25 -0800
From:	Alexandru M Stan <amstan@...omium.org>
To:	Mike Turquette <mturquette@...aro.org>,
	Heiko Stuebner <heiko@...ech.de>,
	Doug Anderson <dianders@...omium.org>,
	addy ke <addy.ke@...k-chips.com>
Cc:	Sonny Rao <sonnyrao@...omium.org>,
	Kever Yang <kever.yang@...k-chips.com>,
	linux-rockchip@...ts.infradead.org,
	linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
	Alexandru M Stan <amstan@...omium.org>, mark.rutland@....com,
	pawel.moll@....com, ijc+devicetree@...lion.org.uk,
	linux-kernel@...r.kernel.org, robh+dt@...nel.org,
	galak@...eaurora.org, mark.yao@...k-chips.com
Subject: [PATCH v4 0/2] Add support for the rockchip mmc clock phases using the framework

For now all I have is the getter and setter for the phase, nothing that uses it
(that is ready). You can test the getter like this:
localhost ~ # cat /sys/kernel/debug/clk/clk_summary|grep sample -C 1
sclk_sdio1                            0            0    24000000          0 0
	sdio1_sample                       0            0    12000000          0 0
	sdio1_drv                          0            0    12000000          0 90
--
	sclk_sdmmc                      1            1   297000000          0 0
		sdmmc_sample                 0            0   148500000          0 134
		sdmmc_drv                    0            0   148500000          0 90
--
	sclk_sdio0                      1            1   100000000          0 0
		sdio0_sample                 0            0    50000000          0 0
		sdio0_drv                    0            0    50000000          0 90
	sclk_emmc                       1            1   100000000          0 0
		emmc_sample                  0            0    50000000          0 0
		emmc_drv                     0            0    50000000          0 180

Next thing that will come is some dts changes that will make use of these new
clocks, and eventually mmc code will be changed to tune with these clocks. You
can see some WIP on https://chromium-review.googlesource.com/#/c/227240


Changes in v4:
- Changed set_phase to 22.5 increments, it seems better for tuning, better at
splitting up big ranges where we might have used an iffy phase from the middle.
- renamed ROCKCHIP_MMC_DELAY_ELEMENT_PSEC
- saner mask of 0x07ff
- only set ROCKCHIP_MMC_DELAYNUM_OFFSET when we need it

Changes in v3:
- renamed everything internal from phase to just mmc_clock or mmc
- added RK3288_MMC_CLKGEN_DIV instead of the magic number
- added new paragraph to commit message

Changes in v2:
- fixed my cc/to list
- removed dangling #DEFINE DEBUG

Alexandru M Stan (2):
  clk: rockchip: add bindings for the mmc clocks
  clk: rockchip: Add support for the mmc clock phases using the
    framework

 drivers/clk/rockchip/Makefile          |   1 +
 drivers/clk/rockchip/clk-mmc-phase.c   | 154 +++++++++++++++++++++++++++++++++
 drivers/clk/rockchip/clk-rk3288.c      |  12 +++
 drivers/clk/rockchip/clk.c             |   8 ++
 drivers/clk/rockchip/clk.h             |  23 +++++
 include/dt-bindings/clock/rk3288-cru.h |  10 +++
 6 files changed, 208 insertions(+)
 create mode 100644 drivers/clk/rockchip/clk-mmc-phase.c

-- 
2.2.0.rc0.207.ga3a616c

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