linux-kernel - [PATCH V4 13/16] MIPS: BMIPS: Flush the readahead cache after DMA

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Message-Id: <1417149142-3756-14-git-send-email-cernekee@gmail.com>
Date:	Thu, 27 Nov 2014 20:32:19 -0800
From:	Kevin Cernekee <cernekee@...il.com>
To:	ralf@...ux-mips.org
Cc:	f.fainelli@...il.com, jfraser@...adcom.com, dtor@...omium.org,
	tglx@...utronix.de, jason@...edaemon.net, jogo@...nwrt.org,
	arnd@...db.de, computersforpeace@...il.com,
	linux-mips@...ux-mips.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH V4 13/16] MIPS: BMIPS: Flush the readahead cache after DMA

BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2.  During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC.  To
avoid possible coherency problems, flush the RAC upon DMA completion.

Signed-off-by: Kevin Cernekee <cernekee@...il.com>
---
 arch/mips/mm/dma-default.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index af5f046e627e..ee6d12cb7588 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -18,6 +18,7 @@
 #include <linux/highmem.h>
 #include <linux/dma-contiguous.h>
 
+#include <asm/bmips.h>
 #include <asm/cache.h>
 #include <asm/cpu-type.h>
 #include <asm/io.h>
@@ -69,6 +70,18 @@ static inline struct page *dma_addr_to_page(struct device *dev,
  */
 static inline int cpu_needs_post_dma_flush(struct device *dev)
 {
+	if (boot_cpu_type() == CPU_BMIPS3300 ||
+	    boot_cpu_type() == CPU_BMIPS4350 ||
+	    boot_cpu_type() == CPU_BMIPS4380) {
+		void __iomem *cbr = BMIPS_GET_CBR();
+
+		/* Flush stale data out of the readahead cache */
+		__raw_writel(0x100, cbr + BMIPS_RAC_CONFIG);
+		__raw_readl(cbr + BMIPS_RAC_CONFIG);
+
+		return 0;
+	}
+
 	return !plat_device_is_coherent(dev) &&
 	       (boot_cpu_type() == CPU_R10000 ||
 		boot_cpu_type() == CPU_R12000 ||
-- 
2.1.0

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