linux-kernel - Re: [PATCH V4 08/16] irqchip: Add new driver for BCM7038-style level 1 interrupt controllers

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Mon, 1 Dec 2014 17:09:04 +0100
From:	Jonas Gorski <jogo@...nwrt.org>
To:	Kevin Cernekee <cernekee@...il.com>
Cc:	Ralf Baechle <ralf@...ux-mips.org>,
	Florian Fainelli <f.fainelli@...il.com>,
	Jon Fraser <jfraser@...adcom.com>,
	Dmitry Torokhov <dtor@...omium.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Jason Cooper <jason@...edaemon.net>,
	Arnd Bergmann <arnd@...db.de>, computersforpeace@...il.com,
	MIPS Mailing List <linux-mips@...ux-mips.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V4 08/16] irqchip: Add new driver for BCM7038-style level
 1 interrupt controllers

On Fri, Nov 28, 2014 at 5:32 AM, Kevin Cernekee <cernekee@...il.com> wrote:
> This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
> it has the following characteristics:
>
>  - 64 to 160+ level IRQs
>  - Atomic set/clear registers
>  - Reasonably predictable register layout (N status words, then N
>    mask status words, then N mask set words, then N mask clear words)
>  - SMP affinity supported on most systems
>  - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
>
> This driver registers one IRQ domain and one IRQ chip to cover all
> instances of the block.  Up to 4 instances of the block may appear, as
> it supports 4-way IRQ affinity on BCM7435.
>
> The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
> is used instead.  So this driver is primarily intended for MIPS STB chips.
>
> Signed-off-by: Kevin Cernekee <cernekee@...il.com>
> ---
>  .../interrupt-controller/brcm,bcm7038-l1-intc.txt  |  52 ++++
>  drivers/irqchip/Kconfig                            |   5 +
>  drivers/irqchip/Makefile                           |   1 +
>  drivers/irqchip/irq-bcm7038-l1.c                   | 335 +++++++++++++++++++++
>  4 files changed, 393 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
>  create mode 100644 drivers/irqchip/irq-bcm7038-l1.c
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
> new file mode 100644
> index 000000000000..cc217b22dccd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
> @@ -0,0 +1,52 @@
> +Broadcom BCM7038-style Level 1 interrupt controller
> +
> +This block is a first level interrupt controller that is typically connected
> +directly to one of the HW INT lines on each CPU.  Every BCM7xxx set-top chip
> +since BCM7038 has contained this hardware.
> +
> +Key elements of the hardware design include:
> +
> +- 64, 96, 128, or 160 incoming level IRQ lines
> +
> +- Most onchip peripherals are wired directly to an L1 input
> +
> +- A separate instance of the register set for each CPU, allowing individual
> +  peripheral IRQs to be routed to any CPU
> +
> +- Atomic mask/unmask operations
> +
> +- No polarity/level/edge settings
> +
> +- No FIFO or priority encoder logic; software is expected to read all
> +  2-5 status words to determine which IRQs are pending
> +
> +Required properties:
> +
> +- compatible: should be "brcm,bcm7038-l1-intc"
> +- reg: specifies the base physical address and size of the registers;
> +  the number of supported IRQs is inferred from the size argument
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: specifies the number of cells needed to encode an interrupt
> +  source, should be 1.
> +- interrupt-parent: specifies the phandle to the parent interrupt controller(s)
> +  this one is cascaded from

I'm not that firm in interrupt controller terminology, but can this be
a level 1 interrupt controller if it has a parent interrupt
controller? Isn't the parent the level 1 interrupt controller? Or
would the parent then be a level 0 interrupt controller? ;-)


Regards,
Jonas
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/