linux-kernel - Re: frequent lockups in 3.18rc4

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Date:	Wed, 3 Dec 2014 23:19:11 +0100 (CET)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Linus Torvalds <torvalds@...ux-foundation.org>
cc:	Dave Jones <davej@...hat.com>, Chris Mason <clm@...com>,
	Mike Galbraith <umgwanakikbuti@...il.com>,
	Ingo Molnar <mingo@...nel.org>,
	Peter Zijlstra <peterz@...radead.org>,
	Dâniel Fraga <fragabr@...il.com>,
	Sasha Levin <sasha.levin@...cle.com>,
	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	John Stultz <john.stultz@...aro.org>
Subject: Re: frequent lockups in 3.18rc4

On Wed, 3 Dec 2014, Linus Torvalds wrote:
> On Wed, Dec 3, 2014 at 12:55 PM, Thomas Gleixner <tglx@...utronix.de> wrote:
> >
> > But it's always negative, which means HPET is always ahead of
> > TSC. That excludes pretty much the clocksource watchdog starvation
> > issue which results in TSC being ahead of HPET due to a HPET
> > wraparound (which takes ~300s).
> 
> Still, I'd be more likely to trust the TSC than the HPET on modern
> machines.. And DaveJ's machine isn't some old one.

Well, that does not explain the softlock watchdog which is solely
relying on the TSC.

> Of course, there's always BIOS games. Can we read the TSC offset
> register and check it being constant (modulo sleep events)?

The kernel does not touch it. Here is a untested hack to verify it on
every local apic timer interrupt. Not nice, but simple :)

Thanks.

	tglx
---
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index ba6cc041edb1..69b0a8143e83 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -554,6 +554,7 @@ static struct clock_event_device lapic_clockevent = {
 	.irq		= -1,
 };
 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
+static DEFINE_PER_CPU(u64, tsc_adjust);
 
 /*
  * Setup the local APIC timer for this CPU. Copy the initialized values
@@ -569,6 +570,13 @@ static void setup_APIC_timer(void)
 		lapic_clockevent.rating = 150;
 	}
 
+	if (this_cpu_has(X86_FEATURE_TSC_ADJUST)) {
+		u64 adj;
+
+		rdmsrl(MSR_IA32_TSC_ADJUST, adj);
+		__this_cpu_write(tsc_adjust, adj);
+	}
+
 	memcpy(levt, &lapic_clockevent, sizeof(*levt));
 	levt->cpumask = cpumask_of(smp_processor_id());
 
@@ -912,6 +920,19 @@ static void local_apic_timer_interrupt(void)
 		return;
 	}
 
+	if (this_cpu_has(X86_FEATURE_TSC_ADJUST)) {
+		u64 adj;
+
+		rdmsrl(MSR_IA32_TSC_ADJUST, adj);
+		if (adj != __this_cpu_read(tsc_adjust)) {
+			pr_err("TSC adjustment on cpu %d changed %llu -> %llu\n",
+			       cpu,
+			       (unsigned long long) __this_cpu_read(tsc_adjust),
+			       (unsigned long long) adj);
+			__this_cpu_write(tsc_adjust, adj);
+		}
+	}
+
 	/*
 	 * the NMI deadlock-detector uses this.
 	 */
--
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