lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Date:	Sun, 07 Dec 2014 21:42:48 +0100
From:	Daniel Lezcano <daniel.lezcano@...aro.org>
To:	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
CC:	Thomas Gleixner <tglx@...utronix.de>,
	Nicolas Pitre <nicolas.pitre@...aro.org>
Subject: [question] on which cpu an interrupt controller will raise an irq
 ?


Hi all,

I am not very familiar with the interrupt subsystem, so sorry if this 
sounds a stupid question.

IIUC, when a interrupt happens on a SMP system and if there is no 
affinity set for it, it is delivered following a scheme decided by the 
interrupt controller.

For example, for the APIC, there is a round robin behaviour, so an 
interrupt will be raised on cpu0, then cpu1, and so on ...

Is there a way to know on which cpu a controller will raise the interrupt ?

Thanks in advance

   -- Daniel



-- 
  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists