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Message-ID: <20141208160316.GM16185@e104818-lin.cambridge.arm.com>
Date: Mon, 8 Dec 2014 16:03:16 +0000
From: Catalin Marinas <catalin.marinas@....com>
To: Arnd Bergmann <arnd@...db.de>
Cc: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Russell King - ARM Linux <linux@....linux.org.uk>,
brcm80211-dev-list <brcm80211-dev-list@...adcom.com>,
linux-wireless <linux-wireless@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Will Deacon <Will.Deacon@....com>,
Hante Meuleman <meuleman@...adcom.com>,
"hauke@...ke-m.de" <hauke@...ke-m.de>,
Arend Van Spriel <arend@...adcom.com>,
David Miller <davem@...emloft.net>,
Marek Szyprowski <m.szyprowski@...sung.com>
Subject: Re: using DMA-API on ARM
On Mon, Dec 08, 2014 at 03:01:32PM +0000, Arnd Bergmann wrote:
> [ 0.000000] PL310 OF: cache setting yield illegal associativity
> [ 0.000000] PL310 OF: -1069781724 calculated, only 8 and 16 legal
> [ 0.000000] L2C-310 enabling early BRESP for Cortex-A9
> [ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9
> [ 0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
> [ 0.000000] L2C-310 cache controller enabled, 16 ways, 256 kB
> [ 0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x4e130001
If the above value is correct, they should make sure bit 22 is set in
AUX_CTRL.
--
Catalin
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