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Message-ID: <d9903a1dee0343c083dc7ec04a70ff99@BN1BFFO11FD015.protection.gbl>
Date: Thu, 11 Dec 2014 09:56:18 +0100
From: Michal Simek <michal.simek@...inx.com>
To: Steffen Trumtrar <s.trumtrar@...gutronix.de>,
atull <atull@...nsource.altera.com>
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Subject: Re: [PATCH v4 2/6] arm: dts: socfpga: add altera fpga manager
On 12/10/2014 06:49 PM, Steffen Trumtrar wrote:
> On Wed, Dec 10, 2014 at 11:25:59AM -0600, atull wrote:
>> On Wed, 10 Dec 2014, Steffen Trumtrar wrote:
>>
>>> Hi!
>>>
>>> On Tue, Dec 09, 2014 at 02:14:46PM -0600, atull@...nsource.altera.com wrote:
>>>> From: Alan Tull <atull@...nsource.altera.com>
>>>>
>>>> Add Altera FGPA manager to device tree.
>>>>
>>>> Signed-off-by: Alan Tull <atull@...nsource.altera.com>
>>>> ---
>>>> arch/arm/boot/dts/socfpga.dtsi | 10 ++++++++++
>>>> 1 file changed, 10 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>>> index 4472fd9..bab98b6 100644
>>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>>> @@ -751,5 +751,15 @@
>>>> compatible = "altr,sys-mgr", "syscon";
>>>> reg = <0xffd08000 0x4000>;
>>>> };
>>>> +
>>>> + hps_0_fpgamgr: fpgamgr@...f706000 {
>>>> + compatible = "altr,fpga-mgr", "simple-bus";
>>>> + reg = <0xFF706000 0x1000
>>>> + 0xFFB90000 0x1000>;
>>>> + interrupts = <0 175 4>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges;
>>>> + };
>>>
>>> The fpgamgr is NOT a bus. You don't need ranges and/or simple-bus.
>>>
>>> Regards,
>>> Steffen
>>
>> Actually, I am going to be using this when I add the DT notification
>> stuff. That stuff is waiting for DT overlays to show up in the main
>> tree.
>>
>> So the choice it to either change this file now, once, or do the minimal
>> changes and have to change it again later.
>>
>
> Yes, that is what I thought. And still, devices can NOT show up
> at the fpgamgr. They show up on the various bridges.
>
> And as far as I understand the DT overlay stuff, you specify in
> the overlay what the parent node will be.
> For i2c this is one of the i2c-hosts, for spi one of the spi-hosts
> and for IP cores in a bitstream one of the bridges.
>
> The fpgamgr is, from my understanding, only responsible for writing
> the bitstream to the FPGA; nothing more.
+1 on this.
I think you can easily decide later where DT overlays will be added.
Thanks,
Michal
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