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Message-ID: <CAD=FV=WdX6YEYSUuahxGPkkyzF2ArFb7mji1PvEXiuDj6Xt1bA@mail.gmail.com>
Date:	Tue, 16 Dec 2014 13:02:01 -0800
From:	Doug Anderson <dianders@...omium.org>
To:	Kever Yang <kever.yang@...k-chips.com>
Cc:	Heiko Stuebner <heiko@...ech.de>,
	Mike Turquette <mturquette@...aro.org>,
	Sonny Rao <sonnyrao@...omium.org>,
	Addy Ke <addy.ke@...k-chips.com>,
	Eddie Cai <cf@...k-chips.com>,
	戴克霖 (Jack) <dkl@...k-chips.com>,
	Tao Huang <huangtao@...k-chips.com>,
	"open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Mark yao <mark.yao@...k-chips.com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] clk: rockchip: add clock ID for usbphy480m_src

Kever,

On Wed, Nov 12, 2014 at 11:22 PM, Kever Yang <kever.yang@...k-chips.com> wrote:
> There are 3 different parent clock from different usbphy,
> all of them are fixed 480MHz, it is not able to auto select
> by clock core to the 2nd and the 3rd parent.
> For different use case for different board, we may need to
> select different usbphy clock out as parent manually.
>
> Add the clock ID for it so that we can use in dts.
>
> Signed-off-by: Kever Yang <kever.yang@...k-chips.com>
> ---
>
>  include/dt-bindings/clock/rk3288-cru.h | 1 +
>  1 file changed, 1 insertion(+)

Aside from clock ID collisions that Heiko can fixup, this looks good to me.

Reviewed-by: Doug Anderson <dianders@...omium.org>
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