lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:	Wed, 17 Dec 2014 11:57:33 -0800
From:	Bjorn Andersson <>
To:	Tim Kryger <>
Cc:	Ulf Hansson <>,
	Alexandre Courbot <>,
	Sachin Kamat <>,
	linux-mmc <>,
	"" <>,
	Alexandre Courbot <>,
	linux-arm-msm <>
Subject: Re: Possible regression with commit 52221610d

On Tue, Dec 16, 2014 at 10:20 PM, Tim Kryger <> wrote:
> On Tue, Dec 16, 2014 at 10:18 AM, Bjorn Andersson <> wrote:
>> We are routing the regulators straight to vdd of the memory and should
>> hence use vmmc to specify this. However unless I actually program 0x29
>> in the Qualcomm sdhci block I get no responses from the card.
>> Which I believe is correct behavior as the SDHC specification [1] says
>> the following about BIT(0) of 0x29:
>> "If this bit is cleared, the Host Controller shall immediately stop
>> driving CMD and DAT[3:0] (tri-state) and drive SDCLK to low level".
>> So I think 52221610d is indeed incorrect.
>> [1]
> Agreed.  Host controllers that fail to implement the required internal
> regulator configured via bits 1-3 of the Power Control Register may
> still follow the specification with regard to bit zero of that same
> register.  The driver should be updated to configure bit zero
> appropriately even when an external regulator is used.

I gave it a spin on one of our Qualcomm 8974 based devices and writing
BIT(0) only seems to be enough.

> If you like, I can propose a patch or if you have one ready, I will be
> happy to review yours.

I'm somewhat puzzled to what benefit 52221610d brings after bringing
back the write of BIT(0). Is it just that we don't hit the BUG() on
non-standard voltages?

The full paragraph regarding BIT(0) reads:

Before setting this bit, the SD Host Driver shall set SD Bus Voltage
Select. If the
Host Controller detects the No Card state, this bit shall be cleared.
If this bit is cleared, the Host Controller shall immediately stop
driving CMD and
DAT[3:0] (tri-state) and drive SDCLK to low level (Refer to Section 2.2.14).

So the Qualcomm HW engineers implemented the last "shall", but if
someone else (what did nvidia do here?) also implemented the first
"shall"s then we're back at needing a full revert of 52221610d.

Non-the-less, feel free to propose a patch and I will give it a test.

To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
More majordomo info at
Please read the FAQ at

Powered by blists - more mailing lists