linux-kernel - Re: [PATCH 4/5] PCI: designware: Add setup bus-related to pcie_host

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Message-id: <000e01d01a7f$47592e20$d60b8a60$%han@samsung.com>
Date:	Thu, 18 Dec 2014 13:58:27 +0900
From:	Jingoo Han <jg1.han@...sung.com>
To:	'Gabriel FERNANDEZ' <gabriel.fernandez@...com>
Cc:	'Arnd Bergmann' <arnd@...db.de>,
	'Rob Herring' <robh+dt@...nel.org>,
	'Pawel Moll' <pawel.moll@....com>,
	'Mark Rutland' <mark.rutland@....com>,
	'Ian Campbell' <ijc+devicetree@...lion.org.uk>,
	'Kumar Gala' <galak@...eaurora.org>,
	'Srinivas Kandagatla' <srinivas.kandagatla@...il.com>,
	'Maxime Coquelin' <maxime.coquelin@...com>,
	'Patrice Chotard' <patrice.chotard@...com>,
	'Russell King' <linux@....linux.org.uk>,
	'Bjorn Helgaas' <bhelgaas@...gle.com>,
	'Mohit Kumar' <mohit.kumar@...com>,
	'Grant Likely' <grant.likely@...aro.org>,
	'Gabriel Fernandez' <gabriel.fernandez@...aro.org>,
	'Fabrice Gasnier' <fabrice.gasnier@...com>,
	'Viresh Kumar' <viresh.kumar@...aro.org>,
	'Thierry Reding' <treding@...dia.com>,
	'Minghuan Lian' <Minghuan.Lian@...escale.com>,
	'Magnus Damm' <damm@...nsource.se>,
	'Will Deacon' <will.deacon@....com>,
	'Tanmay Inamdar' <tinamdar@....com>,
	'Murali Karicheri' <m-karicheri2@...com>,
	'Kishon Vijay Abraham I' <kishon@...com>,
	'Pratyush Anand' <pratyush.anand@...com>,
	'Sachin Kamat' <sachin.kamat@...sung.com>,
	'Andrew Lunn' <andrew@...n.ch>,
	'Liviu Dudau' <Liviu.Dudau@....com>,
	'Srikanth Thokala' <sthokal@...inx.com>,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, kernel@...inux.com,
	linux-pci@...r.kernel.org, 'Lee Jones' <lee.jones@...aro.org>,
	'Jingoo Han' <jg1.han@...sung.com>
Subject: Re: [PATCH 4/5] PCI: designware: Add setup bus-related to pcie_host_ops

On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
> On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
> > ST sti SoCs PCIe IPs are built around DesignWare IP Core.
> > But in these SoCs PCIe IP doesn't support IO.

Hi Gabriel,

I cannot understand how ST sti SoCs PCIe IP does not support I/O.
As far as I know, it cannot be selected by the 'parameter'.
Then, H/W engineers dropped out the I/O control logic?

> >
> > To support this, add setup_bus() to pcie_host_ops.


> >
> > Signed-off-by: Fabrice Gasnier <fabrice.gasnier@...com>
> > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@...aro.org>
> 
> The dw-pcie driver should be able to tell whether the device has
> an I/O space or not, and do the right thing based on that. Don't
> add an implementation specific callback for that.

I agree with Arnd's opinion.

In addition, I have one more question.
Then, if a device that requires I/O region is connected to
PCIe slot of ST sti SoCs PCIe, what will happen?
It just prints error messages?

Best regards,
Jingoo Han

> 
> 	Arnd

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