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Date:	Mon, 22 Dec 2014 14:10:09 -0600
From:	Aravind Gopalakrishnan <>
To:	<>, <>, <>,
	<>, <>, <>,
	<>, <>,
	<>, <>
CC:	<>, <>, <>,
	<>, <>,
	Aravind Gopalakrishnan <>
Subject: [PATCH 0/3] Fix MCE handling for AMD multi-node processors

When a MCE happens that is to be logged onto bank 4 of AMD multi-node
processors, they are reported only to corresponding node base core of
the cpu on which the error occurred.

Refer D18F3x44[NbMcaToMstCpuEn] on BKDGs of Fam10h and later for
clarifications on the reporting of MC4 errors only to NBC MSRs.

We don't have the exception handler wired up to handle this currently.
As a consequence, do_machine_check only runs on the core on which error
occurred and (since according to the BKDGs, reads to MC4_STATUS MSR of
non-NBC will simply RAZ) the exception is ignored for the core.

This is a problem as now we have dropped MCEs.
I tested this on Fam10h and Fam15h using mce_amd_inj and by triggering
a real HW MCE using Boris' new interface; And can confirm the behavior.

This patch set fixes the issue by looking at the NBC MSRs when bank 4
errors happen on AMD multi node processors.

Patch 1: Refactor AMD cpu topology functions so that we can get some
	 relevant info that we need to use in EDAC, MC handler routines
Patch 2: The fix to our problem
Patch 3: Modify mce_amd_inj interfaces to write to only NBC for bank 4
	 errors. Only then will they be picked up for error handling.

Aravind Gopalakrishnan (3):
  x86,amd: Refactor amd cpu topology functions for multi-node processors
  x86, mce: Handle AMD MCE on bank4 on NBC for multi-node processors
  edac, mce_amd_inj: Inject errors only on NBC for bank 4 errors

 arch/x86/include/asm/processor.h |   1 +
 arch/x86/kernel/cpu/amd.c        |  78 ++++++++++++++----
 arch/x86/kernel/cpu/mcheck/mce.c | 167 +++++++++++++++++++++++++++++++++++----
 drivers/edac/mce_amd_inj.c       |  21 ++++-
 4 files changed, 235 insertions(+), 32 deletions(-)


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