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Message-id: <1419335077-31020-4-git-send-email-cw00.choi@samsung.com>
Date: Tue, 23 Dec 2014 20:44:36 +0900
From: Chanwoo Choi <cw00.choi@...sung.com>
To: myungjoo.ham@...sung.com
Cc: kgene.kim@...sung.com, kyungmin.park@...sung.com,
rafael.j.wysocki@...el.com, mark.rutland@....com,
a.kesavan@...sung.com, tomasz.figa@...il.com,
k.kozlowski@...sung.com, cw00.choi@...sung.com,
inki.dae@...sung.com, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org
Subject: [RFC PATCH 3/4] ARM: dts: Add memory bus node for Exynos3250
This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has
following memory buses to translate data between DRAM and eMMC/sub-IPs.
Cc: Kukjin Kim <kgene.kim@...sung.com>
Cc: Myungjoo Ham <myungjoo.ham@...sung.com>
Cc: Kyungmin Park <kyungmin.park@...sung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@...sung.com>
Acked-by: Kyungmin Park <kyungmin.park@...sung.com>
---
arch/arm/boot/dts/exynos3250.dtsi | 137 ++++++++++++++++++++++++++++++++++++++
1 file changed, 137 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 9ed1260..7f20039 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -99,6 +99,143 @@
};
};
+ memory_bus_mif: memory_bus@0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 875000
+ 200000 800000
+ 133000 800000
+ 100000 800000
+ 50000 800000>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 133000
+ 100000
+ 50000>;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus@1 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 400000 950000
+ 200000 950000
+ 133000 925000
+ 100000 850000
+ 80000 850000
+ 50000 850000>;
+
+ status = "disabled";
+
+ blocks {
+ peri_block: memory_bus_block1 {
+ clocks = <&cmu CLK_DIV_ACLK_100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 100000
+ 100000
+ 100000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ display_block: memory_bus_block2 {
+ clocks = <&cmu CLK_DIV_ACLK_160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 160000
+ 100000
+ 80000
+ 80000
+ 50000>;
+ };
+
+ isp_block: memory_bus_block3 {
+ clocks = <&cmu CLK_DIV_ACLK_200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 100000
+ 80000
+ 50000
+ 50000>;
+ };
+
+ gps_block: memory_bus_block4 {
+ clocks = <&cmu CLK_DIV_ACLK_266>;
+ clock-names = "memory-bus";
+ frequency = <
+ 300000
+ 200000
+ 133000
+ 100000
+ 50000
+ 50000>;
+ };
+
+ mcuisp_block: memory_bus_block5 {
+ clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+ clock-names = "memory-bus";
+ frequency = <
+ 400000
+ 200000
+ 50000
+ 50000
+ 50000
+ 50000>;
+ };
+
+ leftbus_block: memory_bus_block6 {
+ clocks = <&cmu CLK_DIV_GDL>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ rightbus_block: memory_bus_block7 {
+ clocks = <&cmu CLK_DIV_GDR>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 133000
+ 100000
+ 100000
+ 100000>;
+ };
+
+ mfc_block: memory_bus_block8 {
+ clocks = <&cmu CLK_SCLK_MFC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 200000
+ 200000
+ 200000
+ 133000
+ 100000
+ 80000>;
+ };
+ };
+ };
+
sysram@...20000 {
compatible = "mmio-sram";
reg = <0x02020000 0x40000>;
--
1.8.5.5
--
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