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Message-ID: <1419410383-6359-5-git-send-email-Ying.Liu@freescale.com>
Date: Wed, 24 Dec 2014 16:39:26 +0800
From: Liu Ying <Ying.Liu@...escale.com>
To: <dri-devel@...ts.freedesktop.org>
CC: <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux@....linux.org.uk>,
<kernel@...gutronix.de>, <p.zabel@...gutronix.de>,
<thierry.reding@...il.com>, <shawn.guo@...aro.org>,
<mturquette@...aro.org>, <airlied@...ux.ie>, <andyshrk@...il.com>,
<stefan.wahren@...e.com>, <a.hajda@...sung.com>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH RFC v5 04/21] ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits definition
This patch adds a macro to define the GPR3 MIPI muxing control register field
shift bits.
Signed-off-by: Liu Ying <Ying.Liu@...escale.com>
---
v4->v5:
* None.
v3->v4:
* None.
v2->v3:
* None.
v1->v2:
* None.
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index ff44374..3b0bed4 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -207,6 +207,7 @@
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4
#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4)
--
2.1.0
--
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