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Date:	Mon, 5 Jan 2015 18:12:00 +0000
From:	Joakim Tjernlund <Joakim.Tjernlund@...nsmode.se>
To:	"christophe.leroy@....fr" <christophe.leroy@....fr>
CC:	"scottwood@...escale.com" <scottwood@...escale.com>,
	"paulus@...ba.org" <paulus@...ba.org>,
	"mpe@...erman.id.au" <mpe@...erman.id.au>,
	"benh@...nel.crashing.org" <benh@...nel.crashing.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>
Subject: Re: [PATCH v3 2/2] powerpc/8xx: use _PAGE_RO instead of _PAGE_RW


On Mon, 2014-12-22 at 11:14 +0100, Christophe Leroy wrote:
> On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
> and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
> 
> Signed-off-by: Christophe Leroy <christophe.leroy@....fr>

Hi Christophe, been meaning to look over all you recent 8xx MMU/TLB patches
but got so little time :(

This is very cool (not sure if there will be a performance gain)  but ..
> 
> 
> 
> diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
> index caf094a..b4e0c3b 100644
> --- a/arch/powerpc/include/asm/pgtable-ppc32.h
> +++ b/arch/powerpc/include/asm/pgtable-ppc32.h
> @@ -178,9 +178,10 @@ static inline unsigned long pte_update(pte_t *p,
>         andc    %1,%0,%5\n\
>         or      %1,%1,%6\n\
>         /* 0x200 == Extended encoding, bit 22 */ \
> -       /* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \
> +       /* Bit 22 has to be 1 when _PAGE_USER is unset and _PAGE_RO is set */ \
>         rlwimi  %1,%1,32-2,0x200\n /* get _PAGE_USER */ \
> -       rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RW */ \
> +       rlwinm  %3,%1,32-1,0x200\n /* get _PAGE_RO */ \
> +       xori    %3,%3,0x200\n \
>         or      %1,%3,%1\n\
>         xori    %1,%1,0x200\n"
>  "      stwcx.  %1,0,%4\n\

... here I expected to loose the existing xori insn instead of adding one?

 Jocke--
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