linux-kernel - Re: [PATCH 2/2] misc: sram: switch to ioremap

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Message-ID: <CAL_JsqJwdr7WvzLqPmui3N4H-wVgSURN6wYD=dm1HyU2HUmXOg@mail.gmail.com>
Date:	Tue, 6 Jan 2015 11:27:41 -0600
From:	Rob Herring <robherring2@...il.com>
To:	Philipp Zabel <p.zabel@...gutronix.de>
Cc:	Abhilash Kesavan <kesavan.abhilash@...il.com>,
	Tony Lindgren <tony@...mide.com>,
	linux-rockchip@...ts.infradead.org,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <Will.Deacon@....com>,
	Santosh Shilimkar <santosh.shilimkar@...com>,
	"heiko@...ech.de" <heiko@...ech.de>,
	"Li.Xiubo@...escale.com" <Li.Xiubo@...escale.com>,
	"shc_work@...l.ru" <shc_work@...l.ru>,
	"nicoleotsuka@...il.com" <nicoleotsuka@...il.com>,
	"arnd@...db.de" <arnd@...db.de>,
	"gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"grant.likely@...aro.org" <grant.likely@...aro.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"corbet@....net" <corbet@....net>,
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	"kernel@...gutronix.de" <kernel@...gutronix.de>,
	"kgene@...nel.org" <kgene@...nel.org>,
	Pawel Moll <Pawel.Moll@....com>
Subject: Re: [PATCH 2/2] misc: sram: switch to ioremap_wc from ioremap

On Tue, Jan 6, 2015 at 10:54 AM, Philipp Zabel <p.zabel@...gutronix.de> wrote:
> Hi Abhilash,
>
> Am Dienstag, den 06.01.2015, 19:57 +0530 schrieb Abhilash Kesavan:
>> >> From the existing dts files, omap, imx, rockchip and exynos seem to be
>> >> the only users of the sram allocator code. I have tested this on
>> >> Exynos5420, Exynos5800 and Exynos7; there is no change in behavior
>> >> seen on these boards. Tested-by for other SoCs would be appreciated.
>> >
>> > Sorry for the delay, these seems to boot OK on omap4, so from that
>> > point of view:
>> >
>> > Tested-by: Tony Lindgren <tony@...mide.com>
>>
>> Thanks a lot for testing this. If someone with imx and rockchip boards
>> could help test this out, then we could look to get this in.
>
> This shouldn't be a problem on i.MX, the coda driver doesn't access SRAM
> from the CPU at all.

Audio buffers are typically (perhaps not in mainline) in SRAM on i.MX
chips which are accessed by CPU and probably mmap'ed to userspace.
That could cause a mismatch in mappings although I would not expect
both the kernel and user space to touch the buffer. That being said, I
don't think this change should cause problems for i.MX (from what I
can remember).

Rob
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