linux-kernel - Re: [PATCH v2 3/3] ARM: dts: berlin: correct BG2Q's SM GPIO location.

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Message-ID: <54AD44E8.5000105@gmail.com>
Date:	Wed, 07 Jan 2015 15:38:32 +0100
From:	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
To:	Jisheng Zhang <jszhang@...vell.com>, robh+dt@...nel.org,
	pawel.moll@....com, mark.rutland@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	linux@....linux.org.uk, antoine.tenart@...e-electrons.com,
	alexandre.belloni@...e-electrons.com,
	thomas.petazzoni@...e-electrons.com
CC:	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/3] ARM: dts: berlin: correct BG2Q's SM GPIO location.

On 26.12.2014 09:58, Jisheng Zhang wrote:
> The gpio4 and gpio5 are in 0xf7fc0000 apb which is located in the SM domain.
> This patch moves gpio4 and gpio5 to the correct location. This patch also
> renames them as the following to match the names we internally used in
> marvell:
> 	gpio4 -> sm_gpio1
> 	gpio5 -> sm_gpio0
> 	porte -> portf
> 	portf -> porte
>
> This also matches what we did for BG2 and BG2CD's SM GPIO.
>
> Signed-off-by: Jisheng Zhang <jszhang@...vell.com>

Jisheng,

please do not add unrelated patches to an existing patch set.

Anyway, applied to berlin/fixes. It will also be Cc'd to stable
from 3.16 onwards due to the broken gpio base address.

Thanks!

Sebastian

> ---
>   arch/arm/boot/dts/berlin2q.dtsi | 60 ++++++++++++++++++++---------------------
>   1 file changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 41a683f..f0ddbec 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -356,36 +356,6 @@
>   				interrupt-parent = <&gic>;
>   				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>   			};
> -
> -			gpio4: gpio@...0 {
> -				compatible = "snps,dw-apb-gpio";
> -				reg = <0x5000 0x400>;
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -
> -				porte: gpio-port@4 {
> -					compatible = "snps,dw-apb-gpio-port";
> -					gpio-controller;
> -					#gpio-cells = <2>;
> -					snps,nr-gpios = <32>;
> -					reg = <0>;
> -				};
> -			};
> -
> -			gpio5: gpio@...0 {
> -				compatible = "snps,dw-apb-gpio";
> -				reg = <0xc000 0x400>;
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -
> -				portf: gpio-port@5 {
> -					compatible = "snps,dw-apb-gpio-port";
> -					gpio-controller;
> -					#gpio-cells = <2>;
> -					snps,nr-gpios = <32>;
> -					reg = <0>;
> -				};
> -			};
>   		};
>
>   		chip: chip-control@...000 {
> @@ -474,6 +444,21 @@
>   			ranges = <0 0xfc0000 0x10000>;
>   			interrupt-parent = <&sic>;
>
> +			sm_gpio1: gpio@...0 {
> +				compatible = "snps,dw-apb-gpio";
> +				reg = <0x5000 0x400>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				portf: gpio-port@5 {
> +					compatible = "snps,dw-apb-gpio-port";
> +					gpio-controller;
> +					#gpio-cells = <2>;
> +					snps,nr-gpios = <32>;
> +					reg = <0>;
> +				};
> +			};
> +
>   			i2c2: i2c@...0 {
>   				compatible = "snps,designware-i2c";
>   				#address-cells = <1>;
> @@ -524,6 +509,21 @@
>   				status = "disabled";
>   			};
>
> +			sm_gpio0: gpio@...0 {
> +				compatible = "snps,dw-apb-gpio";
> +				reg = <0xc000 0x400>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				porte: gpio-port@4 {
> +					compatible = "snps,dw-apb-gpio-port";
> +					gpio-controller;
> +					#gpio-cells = <2>;
> +					snps,nr-gpios = <32>;
> +					reg = <0>;
> +				};
> +			};
> +
>   			sysctrl: pin-controller@...0 {
>   				compatible = "marvell,berlin2q-system-ctrl";
>   				reg = <0xd000 0x100>;
>

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