linux-kernel - Re: [PATCHv3 5/8] ARM: dts: Add memory bus node for Exynos4x12

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Message-id: <36216978.973981421142658259.JavaMail.weblogic@epmlwas05d>
Date:	Tue, 13 Jan 2015 09:51:01 +0000 (GMT)
From:	MyungJoo Ham <myungjoo.ham@...sung.com>
To:	최찬우 <cw00.choi@...sung.com>,
	"kgene@...nel.org" <kgene@...nel.org>
Cc:	박경민 <kyungmin.park@...sung.com>,
	"rafael.j.wysocki@...el.com" <rafael.j.wysocki@...el.com>,
	"mark.rutland@....com" <mark.rutland@....com>,
	ABHILASH KESAVAN <a.kesavan@...sung.com>,
	"tomasz.figa@...il.com" <tomasz.figa@...il.com>,
	Krzysztof Kozlowski <k.kozlowski@...sung.com>,
	Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	대인기 <inki.dae@...sung.com>,
	"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-samsung-soc@...r.kernel.org" 
	<linux-samsung-soc@...r.kernel.org>
Subject: Re: [PATCHv3 5/8] ARM: dts: Add memory bus node for Exynos4x12

>   
>  This patch adds the memory bus node for Exynos4x12 SoC. Exynos4x12 SoC has
> two memory bus to translate data between DRAM and eMMC/sub-IPs.
> 
> Following list specifies the detailed relation between memory bus clock and DMC
> IP in MIF (Memory Interface) block:
> - DMC/ACP clock : DMC (Dynamic Memory Controller)
> 
> Following list specifies the detailed relation between memory bus clock and
> sub-IPs in INT (Internal) block:
> - ACLK100 clock : PERIL/PERIR/MFC(PCLK)
> - ACLK160 clock : CAM/TV/LCD
> - ACLK133 clock : FSYS
> - GDL/GDR clock : leftbus/rightbus
> - SCLK_MFC clock : MFC
> 
> Cc: Kukjin Kim <kgene@...nel.org>
> Cc: Myungjoo Ham <myungjoo.ham@...sung.com>
> Cc: Kyungmin Park <kyungmin.park@...sung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@...sung.com>

Acked-by: MyungJoo Ham <myungjoo.ham@...sung.com> for all the other dts file patch with Exynos*.


Off Topic. Not urgent. Just out of curiousity:
  Do you have some idea on how to express voltage variations
with device tree? (not runtime-AVS, but boottime-AVS. runtime-AVS is rather
trivial)

  I think you remember that we often had multiple set of "OPP tables" and
we chose one of them based on the value extracted at boot time in order to
use lower voltage values without deteriorating the reliability.

  Basically, such a feature requires to express multiple OPP lists and let
the kernel choose one of the lists at the boot time, which I doubt the
expressiveness in the current device tree technique.

> ---
>  arch/arm/boot/dts/exynos4x12.dtsi | 121 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 121 insertions(+)
>