linux-kernel - Re: [PATCH v8 2/4] fpga manager: add sysfs interface document

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Message-ID: <20150113162133.2a4d1116@lxorguk.ukuu.org.uk>
Date:	Tue, 13 Jan 2015 16:21:33 +0000
From:	One Thousand Gnomes <gnomes@...rguk.ukuu.org.uk>
To:	Jason Gunthorpe <jgunthorpe@...idianresearch.com>
Cc:	atull <atull@...nsource.altera.com>, Pavel Machek <pavel@...x.de>,
	Pantelis Antoniou <pantelis.antoniou@...sulko.com>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>, hpa@...or.com,
	Michal Simek <monstr@...str.eu>,
	Michal Simek <michal.simek@...inx.com>, rdunlap@...radead.org,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	devicetree@...r.kernel.org, robh+dt@...nel.org,
	Grant Likely <grant.likely@...aro.org>, iws@...o.caltech.edu,
	linux-doc@...r.kernel.org, Mark Brown <broonie@...nel.org>,
	philip@...ister.org, rubini@...dd.com,
	Steffen Trumtrar <s.trumtrar@...gutronix.de>,
	jason@...edaemon.net, kyle.teske@...com, nico@...aro.org,
	Felipe Balbi <balbi@...com>, m.chehab@...sung.com,
	davidb@...eaurora.org, Rob Landley <rob@...dley.net>,
	davem@...emloft.net, cesarb@...arb.net, sameo@...ux.intel.com,
	akpm@...ux-foundation.org,
	Linus Walleij <linus.walleij@...aro.org>, pawel.moll@....com,
	mark.rutland@....com, ijc+devicetree@...lion.org.uk,
	galak@...eaurora.org, devel@...verdev.osuosl.org,
	Alan Tull <delicious.quinoa@...il.com>,
	dinguyen@...nsource.altera.com, yvanderv@...nsource.altera.com
Subject: Re: [PATCH v8 2/4] fpga manager: add sysfs interface document

On Mon, 12 Jan 2015 11:06:08 -0700
Jason Gunthorpe <jgunthorpe@...idianresearch.com> wrote:

> On Sun, Jan 11, 2015 at 10:29:00AM -0600, atull wrote:
> > the FPGA image.  If someone wants there to be only one FPGA image on
> > the FGPA forever, they will probably not be using this framework; their
> > FPGA will probably be loaded before Linux boots up.
> 
> Nonsense, loading the FPGA through Linux is much better

You need both. There are platforms where the FPGA must be loaded to even
boot the OS (for example Linux running an FPGA soft 486 can't run until
the FPGA has the CPU loaded into it.

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