linux-kernel - Re: [PATCH v8 12/14] x86: perf: intel

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Message-ID: <20150113162720.GL25256@twins.programming.kicks-ass.net>
Date:	Tue, 13 Jan 2015 17:27:20 +0100
From:	Peter Zijlstra <peterz@...radead.org>
To:	Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc:	Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
	Robert Richter <rric@...nel.org>,
	Frederic Weisbecker <fweisbec@...il.com>,
	Mike Galbraith <efault@....de>,
	Paul Mackerras <paulus@...ba.org>,
	Stephane Eranian <eranian@...gle.com>,
	Andi Kleen <ak@...ux.intel.com>, kan.liang@...el.com,
	adrian.hunter@...el.com, markus.t.metzger@...el.com,
	mathieu.poirier@...aro.org, acme@...radead.org
Subject: Re: [PATCH v8 12/14] x86: perf: intel_pt: Intel PT PMU driver

On Tue, Jan 13, 2015 at 05:09:58PM +0200, Alexander Shishkin wrote:
> Peter Zijlstra <peterz@...radead.org> writes:
> 
> > On Fri, Nov 14, 2014 at 03:43:45PM +0200, Alexander Shishkin wrote:
> >> +static void pt_event_stop(struct perf_event *event, int mode)
> >> +{
> >> +	struct pt *pt = this_cpu_ptr(&pt_ctx);
> >> +
> >> +	ACCESS_ONCE(pt->handle_nmi) = 0;
> >
> > Why is this needed? Will the hardware still generate interrupts if you
> > stop the PT thing?
> 
> Actually, it turns out that the interrupt condition can race with the
> wrmsr that disables tracing and the PT bit remains set in the global
> status register, causing the next PMI to go into the PT PMI handler,
> which then may decide to re-enable the counter that should be disabled.

OK, please add this information in a suitably placed comment.

Thanks!
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