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Message-ID: <54B58F9B.4050100@linux.intel.com>
Date: Tue, 13 Jan 2015 13:35:23 -0800
From: Dave Hansen <dave.hansen@...ux.intel.com>
To: "Kirill A. Shutemov" <kirill@...temov.name>
CC: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Hugh Dickins <hughd@...gle.com>, linux-mm@...ck.org,
Cyrill Gorcunov <gorcunov@...nvz.org>,
Pavel Emelyanov <xemul@...nvz.org>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] mm: rename mm->nr_ptes to mm->nr_pgtables
On 01/13/2015 12:41 PM, Kirill A. Shutemov wrote:
> On Tue, Jan 13, 2015 at 12:36:23PM -0800, Dave Hansen wrote:
>> On 01/13/2015 11:14 AM, Kirill A. Shutemov wrote:
>>> pgd_t * pgd;
>>> atomic_t mm_users; /* How many users with user space? */
>>> atomic_t mm_count; /* How many references to "struct mm_struct" (users count as 1) */
>>> - atomic_long_t nr_ptes; /* Page table pages */
>>> + atomic_long_t nr_pgtables; /* Page table pages */
>>> int map_count; /* number of VMAs */
>>
>> One more crazy idea...
>>
>> There are 2^9 possible pud pages, 2^18 pmd pages and 2^27 pte pages.
>> That's only 54 bits (technically minus one bit each because the upper
>> half of the address space is for the kernel).
>
> Does this math make sense for all architecures? IA64? Power?
No, the sizes will be different on the other architectures. But, 4k
pages with 64-bit ptes is as bad as it gets, I think. Larger page sizes
mean fewer page tables on powerpc. So the values should at least _fit_
in a long.
Maybe it's not even worth the trouble.
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