linux-kernel - [PATCH v3 04/15] MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register

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Date:	Thu, 15 Jan 2015 16:11:08 +0300
From:	Aleksey Makarov <aleksey.makarov@...iga.com>
To:	<linux-mips@...ux-mips.org>
CC:	<linux-kernel@...r.kernel.org>,
	David Daney <david.daney@...ium.com>,
	Aleksey Makarov <aleksey.makarov@...iga.com>,
	Chandrakala Chavva <cchavva@...iumnetworks.com>,
	Ralf Baechle <ralf@...ux-mips.org>
Subject: [PATCH v3 04/15] MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register

From: Chandrakala Chavva <cchavva@...iumnetworks.com>

Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register,
its a 64-bit wide.

Signed-off-by: Chandrakala Chavva <cchavva@...iumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@...iga.com>
---
 arch/mips/kernel/octeon_switch.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 590ca2d..f0a699d 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -80,7 +80,7 @@
 1:
 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
 	/* Check if we need to store CVMSEG state */
-	mfc0	t0, $11,7	/* CvmMemCtl */
+	dmfc0	t0, $11,7	/* CvmMemCtl */
 	bbit0	t0, 6, 3f	/* Is user access enabled? */
 
 	/* Store the CVMSEG state */
@@ -104,9 +104,9 @@
 	.set reorder
 
 	/* Disable access to CVMSEG */
-	mfc0	t0, $11,7	/* CvmMemCtl */
+	dmfc0	t0, $11,7	/* CvmMemCtl */
 	xori	t0, t0, 0x40	/* Bit 6 is CVMSEG user enable */
-	mtc0	t0, $11,7	/* CvmMemCtl */
+	dmtc0	t0, $11,7	/* CvmMemCtl */
 #endif
 3:
 
-- 
2.2.2

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