linux-kernel - Re: [PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210

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Message-id: <53274700.1254611421660016720.JavaMail.weblogic@epmlwas05d>
Date:	Mon, 19 Jan 2015 09:33:39 +0000 (GMT)
From:	MyungJoo Ham <myungjoo.ham@...sung.com>
To:	최찬우 <cw00.choi@...sung.com>,
	"kgene@...nel.org" <kgene@...nel.org>
Cc:	박경민 <kyungmin.park@...sung.com>,
	"rafael.j.wysocki@...el.com" <rafael.j.wysocki@...el.com>,
	"mark.rutland@....com" <mark.rutland@....com>,
	ABHILASH KESAVAN <a.kesavan@...sung.com>,
	"tomasz.figa@...il.com" <tomasz.figa@...il.com>,
	Krzysztof Kozlowski <k.kozlowski@...sung.com>,
	Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	대인기 <inki.dae@...sung.com>,
	"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-samsung-soc@...r.kernel.org" 
	<linux-samsung-soc@...r.kernel.org>
Subject: Re: [PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210

>   
>  This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has
> one memory bus to translate data between DRAM and eMMC/sub-IPs because
> Exynos4210 must need only one regulator for memory bus.
> 
> Following list specifies the detailed relation between memory bus clock and
> sub-IPs:
> - DMC/ACP clock : DMC (Dynamic Memory Controller)
> - ACLK200 clock : LCD0
> - ACLK100 clock : PERIL/PERIR/MFC(PCLK)
> - ACLK160 clock : CAM/TV/LCD0/LCD1
> - ACLK133 clock : FSYS/GPS
> - GDL/GDR clock : leftbus/rightbus
> - SCLK_MFC clock : MFC
> 
> Cc: Kukjin Kim <kgene@...nel.org>
> Cc: Myungjoo Ham <myungjoo.ham@...sung.com>
> Cc: Kyungmin Park <kyungmin.park@...sung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@...sung.com>

Acked-by: MyungJoo Ham <myungjoo.ham@...sung.com>


Revisiting good old days..?
(good to see the first busfreq driver experimented with is
being DT-nized... :)  )


Cheers,
MyungJoo