linux-kernel - Re: [PATCH] ARM: tegra20: Store CPU "resettable" status in IRAM

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Message-ID: <54BD4C42.6090407@gmail.com>
Date:	Mon, 19 Jan 2015 21:26:10 +0300
From:	Dmitry Osipenko <digetx@...il.com>
To:	Stephen Warren <swarren@...dotorg.org>,
	Thierry Reding <thierry.reding@...il.com>
CC:	Alexandre Courbot <gnurou@...il.com>,
	Peter De Schrijver <pdeschrijver@...dia.com>,
	linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
	stable@...r.kernel.org
Subject: Re: [PATCH] ARM: tegra20: Store CPU "resettable" status in IRAM

19.01.2015 21:00, Dmitry Osipenko пишет:
> 19.01.2015 20:45, Stephen Warren пишет:
>> On 01/19/2015 10:41 AM, Dmitry Osipenko wrote:
>>> 19.01.2015 20:26, Stephen Warren пишет:
>>>> Hopefully this works out. I suppose it's unlikely anyone will be
>>>> running code on
>>>> the AVP upstrem, so any potential conflict with AVP's usage of IRAM
>>>> isn't likely
>>>> to occur.
>>>>
>>> I don't see how it can conflict with AVP code. First KB of IRAM is
>>> reserved for reset handler. Am I missing something?
>>>
>>>  From reset.h:
>>>
>>> /* The first 1K of IRAM is permanently reserved for the CPU reset
>>> handler */
>>
>> I believe "CPU" in that context means AVP CPU. Still, I may not be correct, and
>> to be honest it's likely not too well defined even if that comment seems
>> clear-cut.
>>
> Hmm... Suddenly I recalled that LP2 was always disabled in downstream kernel. I
> remember that I tried it once (couple years ago) and it didn't work, however I
> presume it was just broken. Now I don't feel good with it.
>
Can't generic RAM be used for "resettable" status? Or it will be too slow?...

CPU1 always come up after CPU0, so RAM is already init'ed. Given that CPU0 can't 
be halted with running CPU1, I suppose CPU1 can't be booted first, right? Anyway 
it's not the case for linux.

-- 
Dmitry
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