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Message-ID: <CAOMZO5ADUvWPYVJhKtou-jDrRiiobZ5e=w+FiTX7-Lv+OvbkwA@mail.gmail.com>
Date: Tue, 20 Jan 2015 13:22:59 -0200
From: Fabio Estevam <festevam@...il.com>
To: Russell King - ARM Linux <linux@....linux.org.uk>
Cc: Arend van Spriel <arend@...adcom.com>,
brcm80211-dev-list <brcm80211-dev-list@...adcom.com>,
Arnd Bergmann <arnd@...db.de>,
Catalin Marinas <catalin.marinas@....com>,
linux-wireless <linux-wireless@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Will Deacon <Will.Deacon@....com>,
Hante Meuleman <meuleman@...adcom.com>,
"hauke@...ke-m.de" <hauke@...ke-m.de>,
David Miller <davem@...emloft.net>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Marek Szyprowski <m.szyprowski@...sung.com>
Subject: Re: using DMA-API on ARM
Hi Russell,
On Tue, Dec 9, 2014 at 8:29 AM, Russell King - ARM Linux
<linux@....linux.org.uk> wrote:
> On Tue, Dec 09, 2014 at 11:19:40AM +0100, Arend van Spriel wrote:
>> The issue did not trigger overnight so it seems setting bit 22 <Shared
>> Attribute _Override_ Enable> solves the issue over here. Now the question is
>> how to move forward with this. As I understood from Catalin this patch was
>> not included as it was not considered responsibility of the linux kernel.
>
> It is preferable for firmware to configure the L2 cache appropriately,
> which includes things like the prefetch offsets as well as feature bits
> like bit 22.
>
> I think what I'll do is queue up a patch which adds a warning if bit 22
> is not set, suggesting that firmware is updated to set this bit.
Do you mean something like this?
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -943,6 +943,10 @@ static int __init __l2c_init(const struct
l2c_init_data *data,
pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
data->type, cache_id, aux);
+ if (!(aux & L2C_AUX_CTRL_SHARED_OVERRIDE))
+ pr_warn("%s: L2C_AUX_CTRL_SHARED_OVERRIDE needs to be set by
the bootloader\n",
+ data->type);
+
return 0;
}
--
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