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Message-ID: <A9667DDFB95DB7438FA9D7D576C3D87E0AC262EB@SHSMSX104.ccr.corp.intel.com>
Date: Wed, 21 Jan 2015 08:18:57 +0000
From: "Zhang, Yang Z" <yang.z.zhang@...el.com>
To: Wincy Van <fanwenyi0529@...il.com>,
Paolo Bonzini <pbonzini@...hat.com>,
"gleb@...nel.org" <gleb@...nel.org>
CC: "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Wanpeng Li <wanpeng.li@...ux.intel.com>,
Jan Kiszka <jan.kiszka@....de>
Subject: RE: [PATCH 1/5] KVM: nVMX: Make nested control MSRs per-cpu.
Wincy Van wrote on 2015-01-16:
> To enable nested apicv support, we need per-cpu vmx control MSRs:
> 1. If in-kernel irqchip is enabled, we can enable nested
> posted interrupt, we should set posted intr bit in the
> nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled,
> we can not enable nested posted interrupt, the posted intr bit in
> the nested_vmx_pinbased_ctls_high will be cleared.
> Since there would be different settings about in-kernel irqchip
> between VMs, different nested control MSRs are needed.
I'd suggest you to check irqchip_in_kernel() instead moving the whole ctrl msr to per vcpu.
Best regards,
Yang
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