lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <1422395155-16511-1-git-send-email-james.hogan@imgtec.com>
Date:	Tue, 27 Jan 2015 21:45:46 +0000
From:	James Hogan <james.hogan@...tec.com>
To:	Ralf Baechle <ralf@...ux-mips.org>, <linux-mips@...ux-mips.org>
CC:	<linux-kernel@...r.kernel.org>,
	James Hogan <james.hogan@...tec.com>,
	Andrew Bresticker <abrestic@...omium.org>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	Ingo Molnar <mingo@...hat.com>,
	Jason Cooper <jason@...edaemon.net>,
	Paul Mackerras <paulus@...ba.org>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Robert Richter <rric@...nel.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	<oprofile-list@...ts.sf.net>
Subject: [PATCH 0/9] MIPS: Allow shared IRQ for timer & perf counter

The main purpose of this patchset is to enable the MIPS CPU IRQ lines to
be shared by the timer handler and performance counter handlers on MIPS
r2+ cores, i.e. using IRQF_SHARED instead of having the timer handler
directly call the perf counter handler.

This will allow the handling of local IRQs to scale to a 3rd IRQ for the
fast debug channel (FDC), which would get pretty messy using calls
between handlers as each interrupt can be arbitrarily routed to
different or shared IRQ lines since MIPS r2.

Pre-r2 IRQF_SHARED cannot be used as we aren't guaranteed to have
individual local interrupt pending bits in CP0_Cause, so the interrupt
conditions must be checked in the right order by the cevt-r4k handler.


Patches 1-5 are minor refactors for stuff noticed along the way and
shouldn't have any functional change by themselves.

Patches 6-8 convert each of the timer and perf handlers to use
compatible IRQ flags, and finally patch 9 makes the switch so that the
interrupt line numbers may be the same on r2.


Cc: Ralf Baechle <ralf@...ux-mips.org>
Cc: Andrew Bresticker <abrestic@...omium.org>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>
Cc: Ingo Molnar <mingo@...hat.com>
Cc: Jason Cooper <jason@...edaemon.net>
Cc: Paul Mackerras <paulus@...ba.org>
Cc: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc: Robert Richter <rric@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: linux-mips@...ux-mips.org
Cc: oprofile-list@...ts.sf.net


James Hogan (9):
  MIPS: cevt-r4k: Move handle_perf_irq() out of header
  MIPS: Use CAUSEF_TI, CAUSEF_PCI constants
  MIPS: Remove redundant IPTI==IPPCI logic
  irqchip: mips-gic: Fix typo in comment
  irqchip: mips-gic: Add missing definitions for FDC IRQ
  MIPS: cevt-r4k: Make interrupt handler shared
  MIPS: perf: Allow sharing IRQ with timer
  MIPS: OProfile: Allow sharing IRQ with timer
  MIPS: Allow shared IRQ for timer & perf counter

 arch/mips/include/asm/cevt-r4k.h     | 19 -------------------
 arch/mips/kernel/cevt-r4k.c          | 28 ++++++++++++++++++++++++++--
 arch/mips/kernel/perf_event_mipsxx.c | 11 ++++++-----
 arch/mips/kernel/traps.c             |  2 --
 arch/mips/oprofile/op_model_mipsxx.c | 10 ++++++----
 drivers/irqchip/irq-mips-gic.c       |  2 +-
 include/linux/irqchip/mips-gic.h     |  6 ++++++
 7 files changed, 45 insertions(+), 33 deletions(-)

-- 
2.0.5

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ