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Message-ID: <A9667DDFB95DB7438FA9D7D576C3D87E0AC2E2F6@SHSMSX104.ccr.corp.intel.com>
Date: Thu, 29 Jan 2015 03:17:32 +0000
From: "Zhang, Yang Z" <yang.z.zhang@...el.com>
To: Wincy Van <fanwenyi0529@...il.com>,
Paolo Bonzini <pbonzini@...hat.com>,
"gleb@...nel.org" <gleb@...nel.org>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
Wanpeng Li <wanpeng.li@...ux.intel.com>,
Jan Kiszka <jan.kiszka@....de>
Subject: RE: [PATCH v4 0/6] KVM: nVMX: Enable nested apicv support
Wincy Van wrote on 2015-01-28:
> v1 ---> v2:
> Use spin lock to ensure vmcs12 is safe when doing nested
> posted interrupt delivery.
> v2 ---> v3:
> 1. Add a new field in nested_vmx to avoid the spin lock in v2.
> 2. Drop send eoi to L1 when doing nested interrupt delivery.
> 3. Use hardware MSR bitmap to enable nested virtualize x2apic
> mode.
> v3 ---> v4:
> 1. Optimize nested msr bitmap merging.
> 2. Allocate nested msr bitmap only when nested == 1.
> 3. Inline the nested vmx control checking functions.
This version looks good to me. Only minor comment: EXIT_REASON_APIC_WRITE vmexit is introduced by apic register virtualization not virtual interrupt delivery, so it's better add it in 4th patch not 5th patch.(If no other comments, I guess Paolo can help do it when applying it).
Reviewed-by: Yang Zhang <yang.z.zhang@...el.com>
> Wincy Van (6):
> KVM: nVMX: Use hardware MSR bitmap
> KVM: nVMX: Enable nested virtualize x2apic mode
> KVM: nVMX: Make nested control MSRs per-cpu
> KVM: nVMX: Enable nested apic register virtualization
> KVM: nVMX: Enable nested virtual interrupt delivery
> KVM: nVMX: Enable nested posted interrupt processing
> arch/x86/kvm/vmx.c | 580
> +++++++++++++++++++++++++++++++++++++++++++--------- 1 files changed,
> 480 insertions(+), 100 deletions(-)
Best regards,
Yang
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