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Message-Id: <1422612241-12944-2-git-send-email-svarbanov@mm-sol.com>
Date: Fri, 30 Jan 2015 12:03:59 +0200
From: Stanimir Varbanov <svarbanov@...sol.com>
To: Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Kumar Gala <galak@...eaurora.org>,
Grant Likely <grant.likely@...aro.org>,
Ian Campbell <ijc+devicetree@...lion.org.uk>
Cc: linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
Bjorn Andersson <bjorn.andersson@...ymobile.com>,
Joonwoo Park <joonwoop@...eaurora.org>,
Andy Gross <agross@...eaurora.org>,
Stanimir Varbanov <svarbanov@...sol.com>
Subject: [PATCH v3 1/3] pinctrl: qcom: increase variable size for register offsets
From: Joonwoo Park <joonwoop@...eaurora.org>
On newer TLMM hardware blocks the registers are spread and
we need an offsets upper than 16 bits to address them. Increase
the register offset variables to 32 bits size.
Signed-off-by: Joonwoo Park <joonwoop@...eaurora.org>
Signed-off-by: Stanimir Varbanov <svarbanov@...sol.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@...ymobile.com>
---
drivers/pinctrl/qcom/pinctrl-msm.h | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index b952c4b..54fdd04 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -70,11 +70,11 @@ struct msm_pingroup {
unsigned *funcs;
unsigned nfuncs;
- s16 ctl_reg;
- s16 io_reg;
- s16 intr_cfg_reg;
- s16 intr_status_reg;
- s16 intr_target_reg;
+ u32 ctl_reg;
+ u32 io_reg;
+ u32 intr_cfg_reg;
+ u32 intr_status_reg;
+ u32 intr_target_reg;
unsigned mux_bit:5;
--
1.7.0.4
--
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