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Message-ID: <54CAFF41.2060908@atmel.com>
Date:	Fri, 30 Jan 2015 11:49:21 +0800
From:	Bo Shen <voice.shen@...el.com>
To:	Peter Rosin <peda@...ator.liu.se>, <alsa-devel@...a-project.org>
CC:	Peter Rosin <peda@...ntia.se>, Liam Girdwood <lgirdwood@...il.com>,
	"Mark Brown" <broonie@...nel.org>,
	Jaroslav Kysela <perex@...ex.cz>, Takashi Iwai <tiwai@...e.de>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ASoC: atmel_ssc_dai: Support SND_SOC_DAIFMT_CBM_CFS on
 I2S

Hi Peter,
   Thanks for you patch.

On 01/29/2015 06:16 PM, Peter Rosin wrote:
> From: Peter Rosin <peda@...ntia.se>
>
> Signed-off-by: Peter Rosin <peda@...ntia.se>

Acked-by: Bo Shen <voice.shen@...el.com>

> ---
>   sound/soc/atmel/atmel_ssc_dai.c |   48 +++++++++++++++++++++++++++++++++++++++
>   1 file changed, 48 insertions(+)
>
> diff --git a/sound/soc/atmel/atmel_ssc_dai.c b/sound/soc/atmel/atmel_ssc_dai.c
> index 3cd70597d109..f55f3aab8bdd 100644
> --- a/sound/soc/atmel/atmel_ssc_dai.c
> +++ b/sound/soc/atmel/atmel_ssc_dai.c
> @@ -485,6 +485,54 @@ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
>   			| SSC_BF(TFMR_DATLEN, (bits - 1));
>   		break;
>
> +	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS:
> +		/* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */
> +		if (bits > 16 && !ssc->pdata->has_fslen_ext) {
> +			dev_err(dai->dev,
> +				"sample size %d is too large for SSC device\n",
> +				bits);
> +			return -EINVAL;
> +		}
> +
> +		fslen_ext = (bits - 1) / 16;
> +		fslen = (bits - 1) % 16;
> +
> +		rcmr =	  SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
> +			| SSC_BF(RCMR_STTDLY, START_DELAY)
> +			| SSC_BF(RCMR_START, SSC_START_FALLING_RF)
> +			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
> +			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
> +			| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
> +					   SSC_CKS_PIN : SSC_CKS_CLOCK);
> +
> +		rfmr =    SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
> +			| SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
> +			| SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
> +			| SSC_BF(RFMR_FSLEN, fslen)
> +			| SSC_BF(RFMR_DATNB, (channels - 1))
> +			| SSC_BIT(RFMR_MSBF)
> +			| SSC_BF(RFMR_LOOP, 0)
> +			| SSC_BF(RFMR_DATLEN, (bits - 1));
> +
> +		tcmr =	  SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
> +			| SSC_BF(TCMR_STTDLY, START_DELAY)
> +			| SSC_BF(TCMR_START, SSC_START_FALLING_RF)
> +			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
> +			| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
> +			| SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
> +					   SSC_CKS_CLOCK : SSC_CKS_PIN);
> +
> +		tfmr =    SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
> +			| SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE)
> +			| SSC_BF(TFMR_FSDEN, 0)
> +			| SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
> +			| SSC_BF(TFMR_FSLEN, fslen)
> +			| SSC_BF(TFMR_DATNB, (channels - 1))
> +			| SSC_BIT(TFMR_MSBF)
> +			| SSC_BF(TFMR_DATDEF, 0)
> +			| SSC_BF(TFMR_DATLEN, (bits - 1));
> +		break;
> +
>   	case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
>   		/*
>   		 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
>

Best Regards,
Bo Shen
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