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Message-ID: <1422983857.12631.2.camel@aoeu.buserror.net>
Date: Tue, 3 Feb 2015 11:17:37 -0600
From: Scott Wood <scottwood@...escale.com>
To: Christophe Leroy <christophe.leroy@....fr>
CC: Benjamin Herrenschmidt <benh@...nel.crashing.org>,
Paul Mackerras <paulus@...ba.org>,
Michael Ellerman <mpe@...erman.id.au>,
<linux-kernel@...r.kernel.org>, <linuxppc-dev@...ts.ozlabs.org>,
"Joakim Tjernlund" <joakim.tjernlund@...nsmode.se>
Subject: Re: [PATCH v3 00/11] powerpc8xx: Further optimisation of TLB
handling
On Tue, 2015-02-03 at 12:38 +0100, Christophe Leroy wrote:
> This patchset provides a further optimisation of TLB handling in the 8xx.
> Main changes are based on:
> - Using processor handling of PGD/PTE Validity bits instead of testing ourselves
> the entries validity
> - Aligning PGD address to allow direct bit manipulation
> - Not saving registers like CR when not needed
>
> It also adds support to any TASK_SIZE
Please respin with just the changes that haven't already been applied to
my next branch.
-Scott
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