linux-kernel - Re: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

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Message-ID: <20150204091317.GA5492@lukather>
Date:	Wed, 4 Feb 2015 10:13:17 +0100
From:	Maxime Ripard <maxime.ripard@...e-electrons.com>
To:	Brian Norris <computersforpeace@...il.com>
Cc:	Gregory Clement <gregory.clement@...e-electrons.com>,
	Jason Cooper <jason@...edaemon.net>,
	Andrew Lunn <andrew@...n.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
	Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>,
	linux-mtd@...ts.infradead.org,
	Boris Brezillon <boris@...e-electrons.com>,
	Thomas Petazzoni <thomas@...e-electrons.com>,
	linux-arm-kernel@...ts.infradead.org,
	Tawfik Bayouk <tawfik@...vell.com>,
	Nadav Haklai <nadavh@...vell.com>,
	Lior Amsalem <alior@...vell.com>, linux-kernel@...r.kernel.org,
	Sudhakar Gundubogula <sudhakar@...vell.com>,
	Seif Mazareeb <seif@...vell.com>, stable@...r.kernel.org
Subject: Re: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

Hi Brian,

On Mon, Jan 26, 2015 at 03:56:03PM +0100, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
> 
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we have to make sure that the
> RDDREQ bit is set in the NDSR register.
> 
> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
> SoCs, when a read on a newly erased page would end up in the driver reporting a
> timeout from the NAND.
> 
> Cc: <stable@...r.kernel.org> # v3.14
> Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com>

Any chance for this fix to come in 3.19?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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