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Message-Id: <1423388966-8204-1-git-send-email-tolga.ceylan@gmail.com>
Date: Sun, 8 Feb 2015 01:49:26 -0800
From: Tolga Ceylan <tolga.ceylan@...il.com>
To: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Sanjeev Sharma <sanjeev_sharma@...tor.com>,
Mohammad Jamal <md.jamalmohiuddin@...il.com>,
Loïc Pellegrino <oort10@...il.com>,
Tolga Ceylan <tolga.ceylan@...il.com>,
devel@...verdev.osuosl.org, linux-kernel@...r.kernel.org
Subject: [PATCH 1/1] Staging: rtl8192u: Coding Style Improvements
Lines over 80 were corrected
Signed-off-by: Tolga Ceylan <tolga.ceylan@...il.com>
---
drivers/staging/rtl8192u/r8190_rtl8256.c | 244 ++++++++++++++++++++++---------
1 file changed, 174 insertions(+), 70 deletions(-)
diff --git a/drivers/staging/rtl8192u/r8190_rtl8256.c b/drivers/staging/rtl8192u/r8190_rtl8256.c
index 1868352..3c3e85f 100644
--- a/drivers/staging/rtl8192u/r8190_rtl8256.c
+++ b/drivers/staging/rtl8192u/r8190_rtl8256.c
@@ -37,43 +37,71 @@ void PHY_SetRF8256Bandwidth(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth)
switch (Bandwidth) {
case HT_CHANNEL_WIDTH_20:
- if (priv->card_8192_version == VERSION_819xU_A
- || priv->card_8192_version
- == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
- rtl8192_phy_SetRFReg(dev,
- (RF90_RADIO_PATH_E)eRFPath,
- 0x0b, bMask12Bits, 0x100); /* phy para:1ba */
- rtl8192_phy_SetRFReg(dev,
- (RF90_RADIO_PATH_E)eRFPath,
- 0x2c, bMask12Bits, 0x3d7);
+ /* 8256 D-cut, E-cut, xiong: consider it later! */
+ if (priv->card_8192_version == VERSION_819xU_A
+ || priv->card_8192_version == VERSION_819xU_B) {
+
+ /* phy para:1ba */
+ rtl8192_phy_SetRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ 0x0b, bMask12Bits, 0x100);
+
+ rtl8192_phy_SetRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ 0x2c, bMask12Bits, 0x3d7);
+
+ rtl8192_phy_SetRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ 0x0e, bMask12Bits, 0x021);
+
+ rtl8192_phy_SetRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ 0x14, bMask12Bits, 0x5ab);
+
+ } else {
+ RT_TRACE(COMP_ERR,
+ "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
+ }
+ break;
+ case HT_CHANNEL_WIDTH_20_40:
+ /* 8256 D-cut, E-cut, xiong: consider it later! */
+ if (priv->card_8192_version == VERSION_819xU_A ||
+ priv->card_8192_version == VERSION_819xU_B) {
+
+ /* phy para:3ba */
+ rtl8192_phy_SetRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ 0x0b, bMask12Bits, 0x300);
+
+ rtl8192_phy_SetRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ 0x2c, bMask12Bits, 0x3df);
+
+ rtl8192_phy_SetRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ 0x0e, bMask12Bits, 0x0a1);
+
+ if (priv->chan == 3 || priv->chan == 9)
+ /* I need to set priv->chan whenever
+ * current channel changes
+ */
rtl8192_phy_SetRFReg(dev,
(RF90_RADIO_PATH_E)eRFPath,
- 0x0e, bMask12Bits, 0x021);
+ 0x14, bMask12Bits, 0x59b);
+ else
rtl8192_phy_SetRFReg(dev,
(RF90_RADIO_PATH_E)eRFPath,
0x14, bMask12Bits, 0x5ab);
- } else {
- RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
- }
- break;
- case HT_CHANNEL_WIDTH_20_40:
- if (priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
- rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); /* phy para:3ba */
- rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df);
- rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1);
-
- if (priv->chan == 3 || priv->chan == 9)
- /* I need to set priv->chan whenever current channel changes */
- rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
- else
- rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
- } else {
- RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
- }
- break;
+ } else {
+ RT_TRACE(COMP_ERR,
+ "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
+ }
+ break;
default:
- RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n", Bandwidth);
- break;
+ RT_TRACE(COMP_ERR,
+ "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",
+ Bandwidth);
+ break;
}
}
@@ -113,24 +141,30 @@ void phy_RF8256_Config_ParaFile(struct net_device *dev)
u8 ConstRetryTimes = 5, RetryTimes = 5;
u8 ret = 0;
/* Initialize RF */
- for (eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) {
+ for (eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A;
+ eRFPath < priv->NumTotalRFPath; eRFPath++) {
+
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
continue;
pPhyReg = &priv->PHYRegDef[eRFPath];
/* Joseph test for shorten RF config
- * pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);
+ * pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev,
+ * (RF90_RADIO_PATH_E)eRFPath,
+ * rGlobalCtrl, bMaskDWord);
* ----Store original RFENV control type
*/
switch (eRFPath) {
case RF90_PATH_A:
case RF90_PATH_C:
- u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
+ u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs,
+ bRFSI_RFENV);
break;
case RF90_PATH_B:
case RF90_PATH_D:
- u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
+ u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs,
+ bRFSI_RFENV<<16);
break;
}
@@ -141,16 +175,29 @@ void phy_RF8256_Config_ParaFile(struct net_device *dev)
rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
/* Set bit number of Address and Data for RF register */
- rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 */
- rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? */
- rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
+ /* Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 */
+ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength,
+ 0x0);
+
+ /* Set 0 to 12 bits for Z-serial and 8258,
+ * and set 1 to 14 bits for ???
+ */
+ rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength,
+ 0x0);
+
+ rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0,
+ bMask12Bits, 0xbf);
/* Check RF block (for FPGA platform only)----
- * TODO: this function should be removed on ASIC , Emily 2007.2.2
+ * TODO: this function should be removed on ASIC, Emily 2007.2.2
*/
- if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath)) {
- RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
+ if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF,
+ (RF90_RADIO_PATH_E)eRFPath)) {
+
+ RT_TRACE(COMP_ERR,
+ "PHY_RF8256_Config():Check Radio[%d] Fail!!\n",
+ eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
}
@@ -159,34 +206,79 @@ void phy_RF8256_Config_ParaFile(struct net_device *dev)
/*----Initialize RF fom connfiguration file----*/
switch (eRFPath) {
case RF90_PATH_A:
- while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
- ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
- RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
- RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
+ while (RF3_Final_Value != RegValueToBeCheck
+ && RetryTimes != 0) {
+
+ ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
+ (RF90_RADIO_PATH_E)eRFPath);
+
+ RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ RegOffSetToBeCheck, bMask12Bits);
+
+ RT_TRACE(COMP_RF,
+ "RF %d %d register final value: %x\n",
+ eRFPath, RegOffSetToBeCheck,
+ RF3_Final_Value);
+
RetryTimes--;
}
break;
case RF90_PATH_B:
- while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
- ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
- RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
- RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
+ while (RF3_Final_Value != RegValueToBeCheck
+ && RetryTimes != 0) {
+
+ ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
+ (RF90_RADIO_PATH_E)eRFPath);
+
+ RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ RegOffSetToBeCheck, bMask12Bits);
+
+ RT_TRACE(COMP_RF,
+ "RF %d %d register final value: %x\n",
+ eRFPath, RegOffSetToBeCheck,
+ RF3_Final_Value);
+
RetryTimes--;
}
break;
case RF90_PATH_C:
- while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
- ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
- RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
- RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
+ while (RF3_Final_Value != RegValueToBeCheck
+ && RetryTimes != 0) {
+
+ ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
+ (RF90_RADIO_PATH_E)eRFPath);
+
+ RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ RegOffSetToBeCheck, bMask12Bits);
+
+ RT_TRACE(COMP_RF,
+ "RF %d %d register final value: %x\n",
+ eRFPath, RegOffSetToBeCheck,
+ RF3_Final_Value);
+
RetryTimes--;
}
break;
case RF90_PATH_D:
- while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
- ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
- RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
- RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
+ while (RF3_Final_Value != RegValueToBeCheck
+ && RetryTimes != 0) {
+
+ ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,
+ (RF90_RADIO_PATH_E)eRFPath);
+
+ RF3_Final_Value = rtl8192_phy_QueryRFReg(dev,
+ (RF90_RADIO_PATH_E)eRFPath,
+ RegOffSetToBeCheck,
+ bMask12Bits);
+
+ RT_TRACE(COMP_RF,
+ "RF %d %d register final value: %x\n",
+ eRFPath, RegOffSetToBeCheck,
+ RF3_Final_Value);
+
RetryTimes--;
}
break;
@@ -196,16 +288,20 @@ void phy_RF8256_Config_ParaFile(struct net_device *dev)
switch (eRFPath) {
case RF90_PATH_A:
case RF90_PATH_C:
- rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
+ rtl8192_setBBreg(dev, pPhyReg->rfintfs,
+ bRFSI_RFENV, u4RegValue);
break;
case RF90_PATH_B:
case RF90_PATH_D:
- rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
+ rtl8192_setBBreg(dev, pPhyReg->rfintfs,
+ bRFSI_RFENV<<16, u4RegValue);
break;
}
if (ret) {
- RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
+ RT_TRACE(COMP_ERR,
+ "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!",
+ eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
}
@@ -223,6 +319,7 @@ void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel)
{
u32 TxAGC = 0;
struct r8192_priv *priv = ieee80211_priv(dev);
+
TxAGC = powerlevel;
if (priv->bDynamicTxLowPower == TRUE) {
@@ -247,13 +344,16 @@ void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel)
u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
u8 byte0, byte1, byte2, byte3;
- powerBase0 = powerlevel + priv->TxPowerDiff; /* OFDM rates */
- powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
- powerBase1 = powerlevel; /* MCS rates */
- powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
+ powerBase0 = powerlevel + priv->TxPowerDiff; /* OFDM rates */
+ powerBase0 = (powerBase0<<24) | (powerBase0<<16)
+ | (powerBase0<<8) | powerBase0;
+ powerBase1 = powerlevel; /* MCS rates */
+ powerBase1 = (powerBase1<<24) | (powerBase1<<16)
+ | (powerBase1<<8) | powerBase1;
for (index = 0; index < 6; index++) {
- writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index < 2)?powerBase0:powerBase1);
+ writeVal = priv->MCSTxPowerLevelOriginalOffset[index]
+ + ((index < 2)?powerBase0:powerBase1);
byte0 = (u8)(writeVal & 0x7f);
byte1 = (u8)((writeVal & 0x7f00)>>8);
byte2 = (u8)((writeVal & 0x7f0000)>>16);
@@ -271,19 +371,23 @@ void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel)
/* for tx power track */
if (index == 3) {
- writeVal_tmp = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0;
+ writeVal_tmp = (byte3<<24) | (byte2<<16)
+ | (byte1<<8) | byte0;
priv->Pwr_Track = writeVal_tmp;
}
if (priv->bDynamicTxHighPower == TRUE) {
- /*Add by Jacken 2008/03/06
- *Emily, 20080613. Set low tx power for both MCS and legacy OFDM
+ /* Add by Jacken 2008/03/06
+ * Emily, 20080613.
+ * Set low tx power for both MCS and legacy OFDM
*/
writeVal = 0x03030303;
} else {
- writeVal = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0;
+ writeVal = (byte3<<24) | (byte2<<16)
+ | (byte1<<8) | byte0;
}
- rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
+ rtl8192_setBBreg(dev,
+ RegOffset[index], 0x7f7f7f7f, writeVal);
}
return;
--
2.3.0
--
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