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Message-ID: <54D8596B.1070102@linaro.org>
Date: Mon, 09 Feb 2015 14:53:31 +0800
From: Hanjun Guo <hanjun.guo@...aro.org>
To: Will Deacon <will.deacon@....com>
CC: Catalin Marinas <Catalin.Marinas@....com>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Olof Johansson <olof@...om.net>, Arnd Bergmann <arnd@...db.de>,
Mark Rutland <Mark.Rutland@....com>,
"grant.likely@...aro.org" <grant.likely@...aro.org>,
Lorenzo Pieralisi <Lorenzo.Pieralisi@....com>,
"graeme.gregory@...aro.org" <graeme.gregory@...aro.org>,
Sudeep Holla <Sudeep.Holla@....com>,
"jcm@...hat.com" <jcm@...hat.com>,
Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <Marc.Zyngier@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Mark Brown <broonie@...nel.org>, Rob Herring <robh@...nel.org>,
Robert Richter <rric@...nel.org>,
Randy Dunlap <rdunlap@...radead.org>,
Charles Garcia-Tobin <Charles.Garcia-Tobin@....com>,
"phoenix.liyi@...wei.com" <phoenix.liyi@...wei.com>,
Timur Tabi <timur@...eaurora.org>,
Ashwin Chaugule <ashwinc@...eaurora.org>,
"suravee.suthikulpanit@....com" <suravee.suthikulpanit@....com>,
Mark Langsdorf <mlangsdo@...hat.com>,
"wangyijing@...wei.com" <wangyijing@...wei.com>,
"linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linaro-acpi@...ts.linaro.org" <linaro-acpi@...ts.linaro.org>
Subject: Re: [PATCH v8 15/21] ARM64 / ACPI: Introduce ACPI_IRQ_MODEL_GIC and
register device's gsi
On 2015年02月09日 14:34, Will Deacon wrote:
> On Mon, Feb 02, 2015 at 12:45:43PM +0000, Hanjun Guo wrote:
>> Introduce ACPI_IRQ_MODEL_GIC which is needed for ARM64 as GIC is
>> used, and then register device's gsi with the core IRQ subsystem.
>>
>> acpi_register_gsi() is similar to DT based irq_of_parse_and_map(),
>> since gsi is unique in the system, so use hwirq number directly
>> for the mapping.
>>
>> We are going to implement stacked domains when GICv2m, GICv3, ITS
>> support are added.
>>
>> CC: Marc Zyngier <marc.zyngier@....com>
>> Originally-by: Amit Daniel Kachhap <amit.daniel@...sung.com>
>> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
>> Tested-by: Yijing Wang <wangyijing@...wei.com>
>> Tested-by: Mark Langsdorf <mlangsdo@...hat.com>
>> Tested-by: Jon Masters <jcm@...hat.com>
>> Tested-by: Timur Tabi <timur@...eaurora.org>
>> Signed-off-by: Hanjun Guo <hanjun.guo@...aro.org>
>> ---
>> arch/arm64/kernel/acpi.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++
>> drivers/acpi/bus.c | 3 ++
>> include/linux/acpi.h | 1 +
>> 3 files changed, 77 insertions(+)
>>
>> diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
>> index f80caef..f86a982 100644
>> --- a/arch/arm64/kernel/acpi.c
>> +++ b/arch/arm64/kernel/acpi.c
>> @@ -38,6 +38,12 @@ EXPORT_SYMBOL(acpi_pci_disabled);
>> static int enabled_cpus; /* Processors (GICC) with enabled flag in MADT */
>>
>> /*
>> + * Since we're on ARM, the default interrupt routing model
>> + * clearly has to be GIC.
>> + */
>> +enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_GIC;
>> +
>> +/*
>> * __acpi_map_table() will be called before page_init(), so early_ioremap()
>> * or early_memremap() should be called here to for ACPI table mapping.
>> */
>> @@ -185,6 +191,73 @@ void __init acpi_init_cpus(void)
>> pr_info("%d CPUs enabled, %d CPUs total\n", enabled_cpus, total_cpus);
>> }
>>
>> +int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
>> +{
>> + *irq = irq_find_mapping(NULL, gsi);
>> +
>> + return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
>> +
>> +/*
>> + * success: return IRQ number (>0)
>> + * failure: return =< 0
>> + */
>> +int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
>> +{
>> + unsigned int irq;
>> + unsigned int irq_type;
>> +
>> + /*
>> + * ACPI have no bindings to indicate SPI or PPI, so we
>> + * use different mappings from DT in ACPI.
>> + *
>> + * For FDT
>> + * PPI interrupt: in the range [0, 15];
>> + * SPI interrupt: in the range [0, 987];
>> + *
>> + * For ACPI, GSI should be unique so using
>> + * the hwirq directly for the mapping:
>> + * PPI interrupt: in the range [16, 31];
>> + * SPI interrupt: in the range [32, 1019];
>> + */
>> +
>> + if (trigger == ACPI_EDGE_SENSITIVE &&
>> + polarity == ACPI_ACTIVE_LOW)
>> + irq_type = IRQ_TYPE_EDGE_FALLING;
>> + else if (trigger == ACPI_EDGE_SENSITIVE &&
>> + polarity == ACPI_ACTIVE_HIGH)
>> + irq_type = IRQ_TYPE_EDGE_RISING;
>> + else if (trigger == ACPI_LEVEL_SENSITIVE &&
>> + polarity == ACPI_ACTIVE_LOW)
>> + irq_type = IRQ_TYPE_LEVEL_LOW;
>> + else if (trigger == ACPI_LEVEL_SENSITIVE &&
>> + polarity == ACPI_ACTIVE_HIGH)
>> + irq_type = IRQ_TYPE_LEVEL_HIGH;
>> + else
>> + irq_type = IRQ_TYPE_NONE;
>> +
>> + /*
>> + * Since only one GIC is supported in ACPI 5.0, we can
>> + * create mapping refer to the default domain
>> + */
>> + irq = irq_create_mapping(NULL, gsi);
>> + if (!irq)
>> + return irq;
>> +
>> + /* Set irq type if specified and different than the current one */
>> + if (irq_type != IRQ_TYPE_NONE &&
>> + irq_type != irq_get_trigger_type(irq))
>> + irq_set_irq_type(irq, irq_type);
>> + return irq;
>> +}
>> +EXPORT_SYMBOL_GPL(acpi_register_gsi);
>> +
>> +void acpi_unregister_gsi(u32 gsi)
>> +{
>> +}
>> +EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
>> +
>> static int __init acpi_parse_fadt(struct acpi_table_header *table)
>> {
>> struct acpi_table_fadt *fadt = (struct acpi_table_fadt *)table;
>
> Does this code *have* to sit under arch/arm64? I can't see anything
> architecture-specific about it and the bulk of the functions map directly
> onto irq domain callbacks. I know that the answer is probably "we can fix
> that in the future", but it doesn't seem like a huge amount of effort to
> get the right abstractions in place from the beginning so that we don't
> have to churn this stuff later on.
Do you mean move acpi_register_gsi()/acpi_unregister_gsi() to irqdomain
related file?
Since x86 and IA64 have their arch specific acpi_register_gsi()
/acpi_unregister_gsi(), we will got compile errors on x86 and IA64
platforms.
Thanks
Hanjun
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