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Date:	Wed, 11 Feb 2015 13:11:15 +0100
From:	Borislav Petkov <bp@...en8.de>
To:	Dave Hansen <dave@...1.net>
Cc:	linux-kernel@...r.kernel.org, x86@...nel.org,
	dave.hansen@...ux.intel.com
Subject: Re: [RFC][PATCH] x86: nit: wrong page size in init_memory_mapping()
 printks

On Tue, Feb 10, 2015 at 01:20:30PM -0800, Dave Hansen wrote:
> 
> From: Dave Hansen <dave.hansen@...ux.intel.com>
> 
> With 32-bit non-PAE kernels, we have 2 page sizes available
> (at most): 4k and 4M.
> 
> Enabling PAE replaces that 4M size with a 2M one (which 64-bit
> systems use too).
> 
> But, when booting a 32-bit non-PAE kernel, in one of our
> early-boot printouts, we say:
> 
> [    0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
> [    0.000000]  [mem 0x00000000-0x000fffff] page 4k
> [    0.000000] init_memory_mapping: [mem 0x37000000-0x373fffff]
> [    0.000000]  [mem 0x37000000-0x373fffff] page 2M
> [    0.000000] init_memory_mapping: [mem 0x00100000-0x36ffffff]
> [    0.000000]  [mem 0x00100000-0x003fffff] page 4k
> [    0.000000]  [mem 0x00400000-0x36ffffff] page 2M
> [    0.000000] init_memory_mapping: [mem 0x37400000-0x377fdfff]
> [    0.000000]  [mem 0x37400000-0x377fdfff] page 4k
> 
> Which is obviously wrong.  There is no 2M page available.  This
> is probably because of a badly-named variable: in the map_range
> code: PG_LEVEL_2M.
> 
> Instead of renaming all the PG_LEVEL_2M's.  This patch just
> fixes the printout:
> 
> [    0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
> [    0.000000]  [mem 0x00000000-0x000fffff] page 4k
> [    0.000000] init_memory_mapping: [mem 0x37000000-0x373fffff]
> [    0.000000]  [mem 0x37000000-0x373fffff] page 4M
> [    0.000000] init_memory_mapping: [mem 0x00100000-0x36ffffff]
> [    0.000000]  [mem 0x00100000-0x003fffff] page 4k
> [    0.000000]  [mem 0x00400000-0x36ffffff] page 4M
> [    0.000000] init_memory_mapping: [mem 0x37400000-0x377fdfff]
> [    0.000000]  [mem 0x37400000-0x377fdfff] page 4k
> [    0.000000] BRK [0x03206000, 0x03206fff] PGTABLE
> 
> 
> Signed-off-by: Dave Hansen <dave.hansen@...ux.intel.com>

Looks ok to me considering that we're missing a PG_LEVEL_4M thing
completely which would need to be handled depending on X86_PAE and CR4
PSE and PAE bits. Probably not worth the trouble though.

Acked-by: Borislav Petkov <bp@...e.de>

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
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