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Message-ID: <20150212135440.GG20811@tbergstrom-lnx.Nvidia.com>
Date: Thu, 12 Feb 2015 15:54:40 +0200
From: Peter De Schrijver <pdeschrijver@...dia.com>
To: Mikko Perttunen <mikko.perttunen@...si.fi>
CC: <swarren@...dotorg.org>, <thierry.reding@...il.com>,
<gnurou@...il.com>, <rjw@...ysocki.net>, <viresh.kumar@...aro.org>,
<mturquette@...aro.org>, <pwalmsley@...dia.com>,
<vinceh@...dia.com>, <pgaikwad@...dia.com>,
<linux-kernel@...r.kernel.org>, <linux-pm@...r.kernel.org>,
<linux-tegra@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <tuomas.tynkkynen@....fi>,
Tuomas Tynkkynen <ttynkkynen@...dia.com>
Subject: Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL
clocksource
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
> From: Tuomas Tynkkynen <ttynkkynen@...dia.com>
>
> The DFLL is the main clocksource for the fast CPU cluster on Tegra124
> and also provides automatic CPU rail voltage scaling as well. The DFLL
> is a separate IP block from the usual Tegra124 clock-and-reset
> controller, so it gets its own node in the device tree.
>
Please add devicetree@...r.kernel.org to the next CC list.
Peter.
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