linux-kernel - [PATCH v6 02/15] of: Document long-ram-code property in nvidia,tegra20-apbmisc

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Message-Id: <1423750042-6535-3-git-send-email-tomeu.vizoso@collabora.com>
Date:	Thu, 12 Feb 2015 15:06:18 +0100
From:	Tomeu Vizoso <tomeu.vizoso@...labora.com>
To:	linux-tegra@...r.kernel.org
Cc:	Javier Martinez Canillas <javier.martinez@...labora.co.uk>,
	Mikko Perttunen <mikko.perttunen@...si.fi>,
	Tomeu Vizoso <tomeu.vizoso@...labora.com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Stephen Warren <swarren@...dotorg.org>,
	Thierry Reding <thierry.reding@...il.com>,
	Alexandre Courbot <gnurou@...il.com>,
	Peter De Schrijver <pdeschrijver@...dia.com>,
	Eduardo Valentin <edubezval@...il.com>,
	Paul Walmsley <paul@...an.com>, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH v6 02/15] of: Document long-ram-code property in nvidia,tegra20-apbmisc

Needed to properly decode the ram code register.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@...labora.com>

---

v3:	* Clarify wording as suggested by Mikko
---
 Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
index 47b205c..4556359 100644
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
@@ -10,3 +10,5 @@ Required properties:
        The second entry gives the physical address and length of the
        registers indicating the strapping options.
 
+Optional properties:
+- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
-- 
1.9.3

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