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Message-ID: <CALszF6D+5mXajUWarwq8M4yL_Nc+x1Bmu4D7_HxDRy2kGRXNVQ@mail.gmail.com>
Date: Fri, 13 Feb 2015 16:59:01 +0100
From: Maxime Coquelin <mcoquelin.stm32@...il.com>
To: Philipp Zabel <p.zabel@...gutronix.de>
Cc: Jonathan Corbet <corbet@....net>, Rob Herring <robh+dt@...nel.org>,
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Subject: Re: [PATCH 12/14] ARM: dts: Introduce STM32F429 MCU
Hi Philipp,
2015-02-13 12:47 GMT+01:00 Philipp Zabel <p.zabel@...gutronix.de>:
> Hi Maxime,
>
> Am Donnerstag, den 12.02.2015, 18:46 +0100 schrieb Maxime Coquelin:
> [...]
>> + soc {
>> + reset_ahb1: reset@...23810 {
>> + #reset-cells = <1>;
>> + compatible = "st,stm32-reset";
>> + reg = <0x40023810 0x4>;
>> + };
>> +
>> + reset_ahb2: reset@...23814 {
>> + #reset-cells = <1>;
>> + compatible = "st,stm32-reset";
>> + reg = <0x40023814 0x4>;
>> + };
>> +
>> + reset_ahb3: reset@...23818 {
>> + #reset-cells = <1>;
>> + compatible = "st,stm32-reset";
>> + reg = <0x40023818 0x4>;
>> + };
>> +
>> + reset_apb1: reset@...23820 {
>> + #reset-cells = <1>;
>> + compatible = "st,stm32-reset";
>> + reg = <0x40023820 0x4>;
>> + };
>> +
>> + reset_apb2: reset@...23824 {
>> + #reset-cells = <1>;
>> + compatible = "st,stm32-reset";
>> + reg = <0x40023824 0x4>;
>> + };
>
> These are mostly consecutive, single registers. I wonder if these are
> part of the same IP block and thus should be grouped together into the
> same reset controller node?
What I could to is to have two instances. One for AHB and one for APB domain.
Doing this, I will have one instance per domain, and only consecutive registers.
Is it fine for you?
Thanks,
Maxime
>
> regards
> Philipp
>
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