linux-kernel - Clarification needed regarding memory barrier

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [day] [month] [year] [list]

Date:	Wed, 18 Feb 2015 20:39:17 +0530
From:	Ayyappa Ch <ayyappa.ch.linux@...il.com>
To:	linux-kernel@...r.kernel.org
Subject: Clarification needed regarding memory barrier

Hello All,

I am reading memory-barrier.txt file as mentioned below.

Please clarify my doubt .
 1) For example if CPU1 got the lock , How PCI bridge can see STORE
*ADDR = 4  before STORE *DATA = 1?

ACQUIRES VS I/O ACCESSES
------------------------

Under certain circumstances (especially involving NUMA), I/O accesses within
two spinlocked sections on two different CPUs may be seen as interleaved by the
PCI bridge, because the PCI bridge does not necessarily participate in the
cache-coherence protocol, and is therefore incapable of issuing the required
read memory barriers.

For example:

CPU 1
===============================
spin_lock(Q)
writel(0, ADDR)
writel(1, DATA);
spin_unlock(Q);

CPU 2
===============================
spin_lock(Q);
writel(4, ADDR);
writel(5, DATA);
spin_unlock(Q);

may be seen by the PCI bridge as follows:

STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5

which would probably cause the hardware to malfunction.

Thanks and regards,
Ayyappa.Ch
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/