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Message-ID: <9bffa4683bd6478993de6bea1d3027af@BN1AFFO11FD048.protection.gbl>
Date: Tue, 24 Feb 2015 15:58:47 +0100
From: Michal Simek <michal.simek@...inx.com>
To: Rob Herring <robherring2@...il.com>,
Michal Simek <michal.simek@...inx.com>
CC: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Sören Brinkmann <soren.brinkmann@...inx.com>,
Robert Richter <rrichter@...ium.com>,
Mark Brown <broonie@...aro.org>,
Eddie Huang <eddie.huang@...iatek.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH] ARM64: Add new Xilinx ZynqMP SoC
On 02/24/2015 03:42 PM, Rob Herring wrote:
> On Tue, Feb 24, 2015 at 1:56 AM, Michal Simek <michal.simek@...inx.com> wrote:
>> Initial version of device tree for Xilinx ZynqMP SoC.
>>
>> Signed-off-by: Michal Simek <michal.simek@...inx.com>
>> Acked-by: Sören Brinkmann <soren.brinkmann@...inx.com>
>> ---
>
> [...]
>
>> + gic: interrupt-controller@...10000 {
>> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>
> gic-400, right?
yep
>
>> + #interrupt-cells = <3>;
>> + reg = <0x0 0xf9010000 0x10000>,
>> + <0x0 0xf9020000 0x20000>,
>> + <0x0 0xf9040000 0x20000>,
>> + <0x0 0xf9060000 0x20000>;
>
> These addresses are wrong if you are doing address swizzling to do 64K
> offsets. We don't really have an answer yet as to what is the right
> way. See the XGene GIC discussion[1].
Is this better for GICC?
<0x0 0xf902f000 0x2000>
Thanks,
Michal
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