linux-kernel - Re: [PATCH v1] clk: qcom: Add MSM8916 Global Clock Controller support

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Message-ID: <54EDC9CD.2000706@codeaurora.org>
Date:	Wed, 25 Feb 2015 18:40:37 +0530
From:	Archit Taneja <architt@...eaurora.org>
To:	Georgi Djakov <georgi.djakov@...aro.org>, sboyd@...eaurora.org
CC:	mturquette@...aro.org, linux-kernel@...r.kernel.org,
	linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v1] clk: qcom: Add MSM8916 Global Clock Controller support

Hi Georgi,

On 02/24/2015 09:19 PM, Georgi Djakov wrote:
> On 02/24/2015 06:49 AM, Archit Taneja wrote:
>> Hi,
> [..]
>>> +
>>> +static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
>>> +    { .src = P_DSI0_PHYPLL_DSI },
>>> +    { }
>>> +};
>>> +
>>> +static struct clk_rcg2 pclk0_clk_src = {
>>> +    .cmd_rcgr = 0x4d084,
>>
>> This should be 0x4d000. Same reason as above.
>>
>>> +    .mnd_width = 8,
>>> +    .hid_width = 5,
>>> +    .parent_map = gcc_xo_gpll0_dsiphy_map,
>>> +    .freq_tbl = ftbl_gcc_mdss_pclk,
>>> +    .clkr.hw.init = &(struct clk_init_data){
>>> +        .name = "pclk0_clk_src",
>>> +        .parent_names = gcc_xo_gpll0_dsiphy,
>>> +        .num_parents = 1,
>>> +        .ops = &clk_rcg2_ops,
>>> +    },
>>> +};
>>> +
>>> +static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
>>> +    F(19200000, P_XO, 1, 0,    0),
>>> +    { }
>>> +};
>>> +
>>> +static struct clk_rcg2 vsync_clk_src = {
>>> +    .cmd_rcgr = 0x4d02c,
>>> +    .hid_width = 5,
>>> +    .parent_map = gcc_xo_gpll0a_map,
>>> +    .freq_tbl = ftbl_gcc_mdss_vsync_clk,
>>> +    .clkr.hw.init = &(struct clk_init_data){
>>> +        .name = "vsync_clk_src",
>>> +        .parent_names = gcc_xo_gpll0a,
>>> +        .num_parents = 2,
>>> +        .ops = &clk_rcg2_ops,
>>> +    },
>>> +};
>>> +
>>

I think we can update the clk ops for pclk0_clk_src and byte0_clk_src to 
clk_pixel_ops and clk_byte_ops respectively too. The set_rate functions 
in these ops have been modified to make it run with DSI PLL.

An Ack by Stephen for this change would be nice, though.

Archit

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