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Message-ID: <CAJhHMCC98dPnx=ng3zp5ZZmzOZkdPXaA1bmcQJuhQj9wb7CRhw@mail.gmail.com>
Date: Fri, 27 Feb 2015 13:25:25 -0500
From: Pranith Kumar <bobby.prani@...il.com>
To: Will Deacon <will.deacon@....com>
Cc: Catalin Marinas <Catalin.Marinas@....com>,
Steve Capper <steve.capper@...aro.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH] ARM64: cmpxchg.h: Clear the exclusive access bit on fail
On Fri, Feb 27, 2015 at 5:06 AM, Will Deacon <will.deacon@....com> wrote:
> On Fri, Feb 27, 2015 at 05:46:55AM +0000, Pranith Kumar wrote:
>> In cmpxchg(), we do a load exclusive on an address and upon a comparison fail,
>> we skip the store exclusive instruction. This can result in the exclusive bit
>> still set. If there was a store exclusive after this to the same address, that
>> will see the exclusive bit set. This should not happen.
>
> ... and the problem with that is?
Consider the following scenario:
P0 P1
---------------------------------
ldxr x7, [B] // exclusive bit set
add x7, x7, #1
str ..., [B] // exclusive bit cleared
cmpxchg:
ldxr x0, [B] // exclusive bit set
cmp x0, #0 // cmp fails
b.ne 1f // branch taken
stxr x1, [B] // end of cmpxchg
1:
stxr x7, [B] // succeeds?
The last store exclusive succeeds since the exclusive bit is set which
should not happen. Clearing the exclusive bit before returning from cmpxchg
prevents this happening.
Now I am not sure how likely this will happen. One can argue that a cmpxchg()
will not happen between an external ldxr/stxr. But isn't clearing the exclusive
bit better?
--
Pranith
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