linux-kernel - Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

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Date:	Sat, 28 Feb 2015 01:01:22 -0800
From:	Brian Norris <computersforpeace@...il.com>
To:	Maxime Ripard <maxime.ripard@...e-electrons.com>
Cc:	Gregory Clement <gregory.clement@...e-electrons.com>,
	Jason Cooper <jason@...edaemon.net>,
	Andrew Lunn <andrew@...n.ch>,
	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
	Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>,
	linux-mtd@...ts.infradead.org,
	Boris Brezillon <boris@...e-electrons.com>,
	Thomas Petazzoni <thomas@...e-electrons.com>,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Tawfik Bayouk <tawfik@...vell.com>,
	Nadav Haklai <nadavh@...vell.com>,
	Lior Amsalem <alior@...vell.com>,
	Sudhakar Gundubogula <sudhakar@...vell.com>,
	Seif Mazareeb <seif@...vell.com>, stable@...r.kernel.org
Subject: Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

On Wed, Feb 18, 2015 at 11:32:07AM +0100, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
> 
> However, during a read PIO access, the datasheet specifies that after each 32
> bytes read in that register, when BCH is enabled, we have to make sure that the
> RDDREQ bit is set in the NDSR register.
> 
> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
> SoCs, when a read on a newly erased page would end up in the driver reporting a
> timeout from the NAND.
> 
> Cc: <stable@...r.kernel.org> # v3.14
> Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com>

Pushed this one to linux-mtd.git. I'll try to get it out in the 4.0
cycle. I assume patch 2 (the DT addition) will go through arm-soc.

Brian
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