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Message-Id: <1425213881-5262-14-git-send-email-mikko.perttunen@kapsi.fi>
Date: Sun, 1 Mar 2015 14:44:36 +0200
From: Mikko Perttunen <mikko.perttunen@...si.fi>
To: swarren@...dotorg.org, thierry.reding@...il.com, gnurou@...il.com,
pdeschrijver@...dia.com, rjw@...ysocki.net, viresh.kumar@...aro.org
Cc: mturquette@...aro.org, pwalmsley@...dia.com, vinceh@...dia.com,
pgaikwad@...dia.com, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, tuomas.tynkkynen@....fi,
Tuomas Tynkkynen <ttynkkynen@...dia.com>,
Mikko Perttunen <mikko.perttunen@...si.fi>,
devicetree@...r.kernel.org
Subject: [PATCH v8 13/18] cpufreq: tegra124: Add device tree bindings
From: Tuomas Tynkkynen <ttynkkynen@...dia.com>
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@...dia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@...si.fi>
Cc: devicetree@...r.kernel.org
---
.../bindings/cpufreq/tegra124-cpufreq.txt | 44 ++++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt
diff --git a/Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt
new file mode 100644
index 0000000..b1669fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt
@@ -0,0 +1,44 @@
+Tegra124 CPU frequency scaling driver bindings
+----------------------------------------------
+
+Both required and optional properties listed below must be defined
+under node /cpus/cpu@0.
+
+Required properties:
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - cpu_g: Clock mux for the fast CPU cluster.
+ - cpu_lp: Clock mux for the low-power CPU cluster.
+ - pll_x: Fast PLL clocksource.
+ - pll_p: Auxiliary PLL used during fast PLL rate changes.
+ - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
+- vdd-cpu-supply: Regulator for CPU voltage
+
+Optional properties:
+- clock-latency: Specify the possible maximum transition latency for clock,
+ in unit of nanoseconds.
+
+Example:
+--------
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+
+ clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
+ <&tegra_car TEGRA124_CLK_CCLK_LP>,
+ <&tegra_car TEGRA124_CLK_PLL_X>,
+ <&tegra_car TEGRA124_CLK_PLL_P>,
+ <&dfll>;
+ clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
+ clock-latency = <300000>;
+ vdd-cpu-supply: <&vdd_cpu>;
+ };
+
+ <...>
+};
--
2.3.0
--
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