linux-kernel - Re: [PATCH 2/3] platform/chrome: cros_ec_lpc

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Message-ID: <54F46C80.8050906@collabora.co.uk>
Date:	Mon, 02 Mar 2015 14:58:24 +0100
From:	Javier Martinez Canillas <javier.martinez@...labora.co.uk>
To:	One Thousand Gnomes <gnomes@...rguk.ukuu.org.uk>
CC:	Olof Johansson <olof@...om.net>,
	Doug Anderson <dianders@...omium.org>,
	Bill Richardson <wfrichar@...omium.org>,
	Simon Glass <sjg@...gle.com>,
	Gwendal Grignou <gwendal@...gle.com>,
	Fengguang Wu <fengguang.wu@...el.com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] platform/chrome: cros_ec_lpc - Depend on X86 || COMPILE_TEST

Hello Alan,

On 03/02/2015 02:45 PM, One Thousand Gnomes wrote:
> On Fri, 27 Feb 2015 06:37:49 +0100
> Javier Martinez Canillas <javier.martinez@...labora.co.uk> wrote:
> 
>> The Low Pin Count bus was introduced by Intel and is only used
>> in x86 computers
> 
> The LPC bus is in all but name a slightly chopped down ISA bus. It is not
> x86 specific any more, and indeed there are wishbone/LPC busses used on
> all sorts of systems and processor types.
>

Thanks a lot for the clarification, I didn't know that.
 
> The ChromeOS EC may well be X86 specific but if so please fix the commit
> message accordingly.
>

I'll let the ChromiumOS folks to answer if EC connected through LPC will
only be used in x86 Chromebooks and non-x86 Chromebooks will always use
either SPI or I2C. Or if a non-x86 Chromebook with a EC connected through
LPC may exist in the future.

To know if I should either update the commit message or drop $subject,
since after patch 1/3 the driver builds correctly in other architectures.
 
> Alan
>

Best regards,
Javier
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