linux-kernel - Re: [PATCH v2 1/1] iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Wed, 4 Mar 2015 18:32:58 +0000
From:	Will Deacon <will.deacon@....com>
To:	Baptiste Reynal <b.reynal@...tualopensystems.com>
Cc:	"iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>,
	"kvmarm@...ts.cs.columbia.edu" <kvmarm@...ts.cs.columbia.edu>,
	"tech@...tualopensystems.com" <tech@...tualopensystems.com>,
	Joerg Roedel <joro@...tes.org>,
	"moderated list:ARM SMMU DRIVER" 
	<linux-arm-kernel@...ts.infradead.org>,
	open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 1/1] iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS
 condition

On Wed, Mar 04, 2015 at 03:51:06PM +0000, Baptiste Reynal wrote:
> This patch is a fix to "iommu/arm-smmu: add support for iova_to_phys
> through ATS1PR".
> According to ARM documentation, translation registers are optional even
> in SMMUv1, so ID0_S1TS needs to be checked to verify their presence.
> Also, we check that the domain is a stage-1 domain.
> 
> Signed-off-by: Baptiste Reynal <b.reynal@...tualopensystems.com>
> 
> ---
> v1 -> v2:
> Add domain stage test (Thanks to Will Deacon)
> 
> ---
>  drivers/iommu/arm-smmu.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index fc13dd5..a3adde6 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -1288,10 +1288,13 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
>  		return 0;
>  
>  	spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
> -	if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS)
> +	if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS &&
> +			smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
>  		ret = arm_smmu_iova_to_phys_hard(domain, iova);
> -	else
> +	} else {
>  		ret = ops->iova_to_phys(ops, iova);
> +	}
> +
>  	spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
>  
>  	return ret;
> @@ -1556,7 +1559,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
>  		return -ENODEV;
>  	}
>  
> -	if (smmu->version == 1 || (!(id & ID0_ATOSNS) && (id & ID0_S1TS))) {
> +	if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) {
>  		smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
>  		dev_notice(smmu->dev, "\taddress translation ops\n");

Acked-by: Will Deacon <will.deacon@....com>

Sorry Joerg, but this is the latest in the drip of ARM SMMU fixes for
4.0! Please pick it up with the rest.

Will
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/