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Date: Mon, 9 Mar 2015 20:18:34 +0800
From: Yong Wu <yong.wu@...iatek.com>
To: Daniel Kurtz <djkurtz@...omium.org>
CC: Rob Herring <robh+dt@...nel.org>, Joerg Roedel <joro@...tes.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Robin Murphy <robin.murphy@....com>,
Will Deacon <will.deacon@....com>,
Tomasz Figa <tfiga@...gle.com>,
Lucas Stach <l.stach@...gutronix.de>,
Mark Rutland <mark.rutland@....com>,
Catalin Marinas <catalin.marinas@....com>,
<linux-mediatek@...ts.infradead.org>,
Sasha Hauer <kernel@...gutronix.de>,
<srv_heupstream@...iatek.com>,
"open list:OPEN FIRMWARE AND..." <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"open list:IOMMU DRIVERS" <iommu@...ts.linux-foundation.org>
Subject: Re: [PATCH 5/5] dts: mt8173: Add iommu/smi nodes for mt8173
Dear Daniel,
Thanks very much. I will fix this in next version.
On Sat, 2015-03-07 at 23:20 +0800, Daniel Kurtz wrote:
> Hi Yong,
>
> On Fri, Mar 6, 2015 at 6:48 PM, <yong.wu@...iatek.com> wrote:
> > From: Yong Wu <yong.wu@...iatek.com>
> >
> > This patch add the iommu/larbs nodes for mt8173
> >
> > Signed-off-by: Yong Wu <yong.wu@...iatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 60 ++++++++++++
> > include/dt-bindings/iommu/mt8173-iommu-port.h | 127 ++++++++++++++++++++++++++
> > 2 files changed, 187 insertions(+)
> > create mode 100644 include/dt-bindings/iommu/mt8173-iommu-port.h
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index c2a057f..805a7cd 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -16,6 +16,7 @@
> > #include <dt-bindings/reset-controller/mt8173-resets.h>
> > #include "mt8173-pinfunc.h"
> > #include <dt-bindings/clock/mt8173-clk.h>
> > +#include <dt-bindings/iommu/mt8173-iommu-port.h>
> >
> > / {
> > compatible = "mediatek,mt8173";
> > @@ -249,6 +250,65 @@
> > interrupts = <0 86 8>;
> > clocks = <&uart_clk>;
> > };
> > +
> > + iommu: mmsys_iommu@...05000 {
> > + compatible = "mediatek,mt8173-iommu";
> > + reg = <0 0x10205000 0 0x1000>;
> > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&infrasys INFRA_M4U>;
> > + clock-names = "infra_m4u";
> > + larb = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>;
> > + #iommu-cells = <1>;
> > + };
> > +
> > + larb0:larb@...21000 {
> > + compatible = "mediatek,mt8173-smi-larb";
> > + reg = <0 0x14021000 0 0x1000>;
> > + clocks = <&mmsys MM_SMI_COMMON>, <&mmsys MM_SMI_LARB0>;
> > + clock-names = "larb_sub0", "larb_sub1";
> > + };
> > +
> > + larb1:larb@...10000 {
> > + compatible = "mediatek,mt8173-smi-larb";
> > + reg = <0 0x16010000 0 0x1000>;
> > + clocks = <&mmsys MM_SMI_COMMON>,
> > + <&vdecsys VDEC_CKEN>,
> > + <&vdecsys VDEC_LARB_CKEN>;
> > + clock-names = "larb_sub0", "larb_sub1", "larb_sub2";
> > + };
> > +
> > + larb2:larb@...10000 {
>
> I think this one should be:
> larb2: larb@...01000 {
>
> Also, I am not a devicetree expert, but I believe nodes are usually
> arranged in register order.
> If that is the case, the order, as unfortunate as this looks, should be:
>
> larb0: larb@...21000
> larb4: larb@...27000
> larb2: larb@...01000
> larb1: larb@...10000
> larb3: larb@...01000
> larb5: larb@...01000
>
> -Dan
>
>
> > + compatible = "mediatek,mt8173-smi-larb";
> > + reg = <0 0x15001000 0 0x1000>;
> > + clocks = <&mmsys MM_SMI_COMMON>,
> > + <&imgsys IMG_LARB2_SMI>;
> > + clock-names = "larb_sub0", "larb_sub1";
> > + };
> > +
> > + larb3:larb@...01000 {
> > + compatible = "mediatek,mt8173-smi-larb";
> > + reg = <0 0x18001000 0 0x1000>;
> > + clocks = <&mmsys MM_SMI_COMMON>,
> > + <&vencsys VENC_CKE0>,
> > + <&vencsys VENC_CKE1>;
> > + clock-names = "larb_sub0", "larb_sub1", "larb_sub2";
> > + };
> > +
> > + larb4:larb@...27000 {
> > + compatible = "mediatek,mt8173-smi-larb";
> > + reg = <0 0x14027000 0 0x1000>;
> > + clocks = <&mmsys MM_SMI_COMMON>, <&mmsys MM_SMI_LARB4>;
> > + clock-names = "larb_sub0", "larb_sub1";
> > + };
> > +
> > + larb5:larb@...01000 {
> > + compatible = "mediatek,mt8173-smi-larb";
> > + reg = <0 0x19001000 0 0x1000>;
> > + clocks = <&mmsys MM_SMI_COMMON>,
> > + <&vencltsys VENCLT_CKE0>,
> > + <&vencltsys VENCLT_CKE1>;
> > + clock-names = "larb_sub0", "larb_sub1", "larb_sub2";
> > + };
> > };
> >
> > };
> > --
> > 1.8.1.1.dirty
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