linux-kernel - Re: [PATCH] clk: mediatek: Export CPU mux clocks for CPU frequency control

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Message-ID: <CALx668XpSBj-r6X88AitGuv8LY6cYL4V4Xn4T0hnHaHuL777uw@mail.gmail.com>
Date:	Wed, 11 Mar 2015 15:00:36 +0800
From:	Pi-Cheng Chen <pi-cheng.chen@...aro.org>
To:	Sascha Hauer <s.hauer@...gutronix.de>
Cc:	Mike Turquette <mturquette@...aro.org>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Matthias Brugger <matthias.bgg@...il.com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Henry Chen <henryc.chen@...iatek.com>,
	James Liao <jamesjj.liao@...iatek.com>,
	Chen Fan <fan.chen@...iatek.com>,
	Eddie Huang <eddie.huang@...iatek.com>,
	"Joe.C" <yingjoe.chen@...iatek.com>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	Linaro Kernel Mailman List <linaro-kernel@...ts.linaro.org>,
	linux-mediatek@...ts.infradead.org,
	Viresh Kumar <viresh.kumar@...aro.org>
Subject: Re: [PATCH] clk: mediatek: Export CPU mux clocks for CPU frequency control

On Tue, Mar 10, 2015 at 3:55 PM, Sascha Hauer <s.hauer@...gutronix.de> wrote:
> On Tue, Mar 10, 2015 at 09:53:19AM +0800, Pi-Cheng Chen wrote:
>> On 5 March 2015 at 15:42, Sascha Hauer <s.hauer@...gutronix.de> wrote:
>> >
>> > My suggestion is to take another approach. Implement clk_set_rate for
>> > these muxes and in the set_rate hook:
>> >
>> > - switch mux to intermediate PLL parent
>> > - call clk_set_rate() for the real parent PLL
>> > - switch mux back to real parent PLL
>>
>> Hi Sascha,
>>
>> Thanks for your suggestion. I've tried to take this approach, but there's some
>> issues here.
>>
>> Calling clk_set_rate() inside the set_rate callback of cpumux will cause
>> an infinite recursive calling in the clock framework:
>> mux.set_rate() -> pll.set_rate() -> mux.set_rate -> ...
>
> I don't understand why setting the PLL rate should call into the mux
> set_rate. Are you sure you call clk_set_rate for the mux parent clk?
> I think the general approach should work, drivers/clk/sirf/clk-common.c
> does something similar in cpu_clk_set_rate(). If you like you can send
> me your work in progress state privatly, I'll have a look then.

Thanks for pointing me out the reference. I think I misunderstood the way you
suggested to do it. I'll post the new version once the design including cpufreq
part is finalized.

Best Regards,
Pi-Cheng
>
>>
>> I've also tries to update pll register settings in the set_rate()
>> callback of cpumux,
>> but the PLL clock information will not be correctly updated in this case.
>
> No, that won't work.
>
> Sascha
>
>
> --
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